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1 MX25L6439E high performance serial flash specification MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
2 contents 1. features ........................................................................................................................................................ 4 2. general description ............................................................................................................................... 6 table 1. additional features ....................... ........................................................................................... 6 3. pin configuration ...................................................................................................................................... 7 4. pin description ............................................................................................................................................ 7 5. block diagram ............................................................................................................................................. 8 6. data protection .......................................................................................................................................... 9 table 2. protected area sizes ....................... ....................................................................................... 10 table 3. 4k-bit secured otp defnition ....................... ........................................................................ 11 7. memory organization ............................................................................................................................. 12 table 4. memory organization ............................................................................................................. 12 8. device operation ...................................................................................................................................... 13 9. hold feature .............................................................................................................................................. 14 10. quad peripheral interface (qpi) read mode .............................................................................................. 15 10-1. enable qpi mode .. .............................................................................................................................. 15 10-2. reset qpi mode ... ............................................................................................................................... 15 10-3. fast qpi read mode (f astrdq) ... .................................................................................................... 16 11. command description ........................................................................................................................... 17 table 5. command sets ....................................................................................................................... 17 11-1. w rite enable (wren) ... ....................................................................................................................... 20 11-2. w rite disable (wrdi) ........................................................................................................................... 21 11-3. read identifcation (rdid) ... ................................................................................................................ 22 11-4. read status register (rdsr) ............................................................................................................. 23 11-5. w rite status register (wrsr) ............................................................................................................. 26 table 6. protection modes .................................................................................................................... 27 11-6. read data bytes (read) ... ................................................................................................................. 29 11-7. read data bytes at higher speed (f ast_read) ... ........................................................................... 30 11-8. quad read mode (qread) ... ............................................................................................................. 31 11-9. 4 x i/o read mode (4read) ............................................................................................................... 32 11-10. performance enhance mode ............................................................................................................... 34 11-11. performance enhance mode reset ..................................................................................................... 36 11-12. burst read ... ........................................................................................................................................ 37 11-13. sector erase (se) ................................................................................................................................ 38 11-14. block erase (be) ................................................................................................................................. 39 11-15. block erase (be32k) ........................................................................................................................... 40 11-16. chip erase (ce) ................................................................................................................................... 41 11-17. page program (pp) ............................................................................................................................. 42 11-18. 4 x i/o page program (4pp) ... ............................................................................................................. 43 11-19. continuous program mode (cp mode) ................................................................................................ 46 11-20. deep power-down (dp) ....................................................................................................................... 48 11-21. release from deep power-down (rdp), read electronic signature (res) ... .................................... 49 11-22. read electronic signature (res) ... ..................................................................................................... 50 11-23. qpi id read (qpiid) ........................................................................................................................... 51 table 7. id defnitions ......................................................................................................................... 51 11-24. enter secured otp (enso) ................................................................................................................ 51 MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
3 11-25. exit secured otp (exso) ... ................................................................................................................ 51 11-26. read security register (rdscur) ..................................................................................................... 52 table 8. security register defnition .................................................................................................... 53 11-27. w rite security register (wrscur) ..................................................................................................... 54 11-28. w rite protection selection (wpsel) .................................................................................................... 54 11-29. single block lock/unlock protection (sblk/sbulk) .......................................................................... 58 11-30. read block lock status (rdblock) .................................................................................................. 61 11-31. gang block lock/unlock (gblk/gbulk) ........................................................................................... 62 11-32. program/ erase suspend/ resume ..................................................................................................... 63 11-33. erase suspend .................................................................................................................................... 63 11-34. program suspend ................................................................................................................................ 64 11-35. write-resume ... ................................................................................................................................... 65 11-36. no operation (nop) ............................................................................................................................ 66 11-37. software reset (reset-enable (rsten) and reset (rst)) ............................................................... 66 11-38. reset quad i/o (rstqio) ................................................................................................................... 66 11-39. read sfdp mode (rdsfdp) .............................................................................................................. 67 table 9. signature and parameter identifcation data values ............................................................. 68 table 10. parameter table (0): jedec flash parameter tables ......................................................... 69 table 11. parameter table (1): macronix flash parameter tables ....................................................... 71 12. power-on state ....................................................................................................................................... 73 13. electrical specifications .................................................................................................................. 74 13-1. absolute maximum ra tings ....................................................................................................... 74 13-2. cap acitance ta = 25c, f = 1.0 mhz .............................................................................................. 74 table 12. dc characteristics ..................................................................................................... 76 table 13. ac characteristics ....................... ............................................................................... 77 14. timing analysis ........................................................................................................................................ 79 table 14. power-up timing ....................... .......................................................................................... 81 14-1. initial delivery state .................................................................................................................. 81 15. operating conditions ........................................................................................................................... 82 16. erase and programming performance ........................................................................................ 84 17. data retention ........................................................................................................................................ 84 18. latch-up characteristics .................................................................................................................. 84 19. ordering information .......................................................................................................................... 85 20. part name description ......................................................................................................................... 86 21. package information ............................................................................................................................ 87 22. revision history ..................................................................................................................................... 89 MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
4 64m-bit [x 1 / x 4] cmos mxsmio ? (serial multi i/o) flash memory 1. features general ? serial peripheral interface compatible -- mode 0 and mode 3 ? 67,108,864 x 1 bit structure or 16,777,216 x 4 bits (four i/o mode) structure ? 2048 equal sectors with 4k bytes each - any sector can be erased individually ? 256 equal blocks with 32k bytes each - any block can be erased individually ? 128 equal blocks with 64k bytes each - any block can be erased individually ? power supply operation - 2.7 to 3.6 volt for read, erase, and program operations ? latch-up protected to 100ma from -1v to vcc +1v performance ? high performance vcc = 2.7~3.6v - normal read - 50mhz - fast read - 1 i/o: 104mhz with 8 dummy cycles - 4 i/o: up to 104mhz - confgurable dummy cycle number for 4 i/o read operation - fast read (qpi mode) - 4 i/o: 54mhz with 4 dummy cycles - 4 i/o: 86mhz with 6 dummy cycles - 4 i/o: 104mhz with 8 dummy cycles - fast program time: 0.7ms(typ.) and 3ms(max.)/page (256-byte per page) - byte program time: 12us (typical) - 8/16/32/64 byte w rap-around burst read mode - fast erase time: 30ms (typ.)/sector (4k-byte per sector) ; 0.25s(typ.) /block (64k-byte per block); 20s(typ.) / chip ? low power consumption - low active read current: 19ma(max.) at 104mhz, 10ma(max.) at 33mhz - low active programming current: 15ma (typ.) - low active sector erase current: 10ma (typ.) - low standby current: 15ua (typ.) - deep power-down current: 1ua (typ.) ? typical 100,000 erase/program cycles ? 20 years data retention MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
5 software features ? input data format - 1-byte command code ? advanced security features - bp0-bp3 block group protect - flexible individual block protect when otp wpsel=1 - additional 4k bits secured otp for unique identifer ? auto erase and auto program algorithms - automatically erases and verifes data at selected sector - automatically programs and verifes data at selected page by an internal algorithm that automatically times the program pulse width (any page to be programmed should have page in the erased state frst.) ? status register feature ? command reset ? program/erase suspend ? program/erase resume ? electronic identifcation - jedec 1-byte manufacturer id and 2-byte device id - res command for 1-byte device id ? support serial flash discoverable parameters (sfdp) mode hardware features ? sclk input - serial clock input ? si/sio0 - serial data input or serial data input/output for 4 x i/o mode ? so/sio1 - serial data output or serial data input/output for 4 x i/o mode ? wp#/sio2 - hardware write protection or serial data input/output for 4 x i/o mode ? hold#/sio3 - to pause the device without deselecting the device or serial data input/output for 4 x i/o mode ? package - 8-pin sop (200mil) - 8-pin vsop (200mil) - all devices are rohs compliant and halogen-free MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
6 2. general description MX25L6439E is 64mb bits serial flash memory, which is confgured as 8,388,608 x 8 internally. when it is in four i/o mode, the structure becomes 16,777,216 bits x 4. MX25L6439E feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus while it is in single i/o mode. the three bus signals are a clock input (sclk), a serial data input (si), and a serial data output (so). serial access to the device is enabled by cs# input. MX25L6439E, mxsmio ? (serial multi i/o) fash memory, provides sequential read operation on whole chip and multi-i/o features. when it is in quad i/o mode, the si pin, so pin, wp# pin and hold# pin become sio0 pin, sio1 pin, sio2 pin and sio3 pin for address/dummy bits input and data input/output. after program/erase command is issued, auto program/erase algorithms which program/erase and verify the specifed page or sector/block locations will be executed. program command is executed on byte basis, or page (256 bytes) basis, and erase command is executed on sector (4k-byte), block (32k-byte/64k-byte), or whole chip ba - sis. to provide user with ease of interface, a status register is included to indicate the status of the chip. the status read command can be issued to detect completion status of a program or erase operation via wip bit. when the device is not in operation and cs# is high, it is put in standby mode. the MX25L6439E utilizes macronix's proprietary memory cell, which reliably stores memory contents even after 100,000 program and erase cycles. table 1. additional features numbers of dummy cycles 4 i/o 6 86* 8 104 note: *means default status MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
7 3. pin configuration 4. pin description symbol description cs# chip select si/sio0 serial data input (for 1xi/o)/ serial data input & output (for 4xi/o mode) so/sio1 serial data output (for 1xi/o)/serial data input & output (for 4xi/o mode) sclk clock input wp#/sio2 write protection or serial data input & output (for 4xi/o mode) hold#/ sio3 to pause the device without deselecting the device or serial data input/output for 4 x i/o mode vcc + 3.0v power supply gnd ground note: 1. the hold# pin is internal pull high. 1 2 3 4 cs# so/sio1 wp#/sio2 gnd vcc hold#/sio3 sclk si/sio0 8 7 6 5 8-pin sop (200mil) 8-pin vsop (200mil) 1 2 3 4 cs# so/sio1 wp#/sio2 gnd vcc hold#/sio3 sclk si/sio0 8 7 6 5 MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
8 5. block diagram address generator memory array page buffer y-decoder x-decoder data register sram buffer si/sio0 sclk so/sio1 clock generator state machine mode logic sense amplifier hv generator output buffer cs# wp#/sio2 hold#/sio3 MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
9 6. data protection during power transition, there may be some false system level signals which result in inadvertent erasure or pro - gramming. the device is designed to protect itself from these accidental write cycles. the state machine will be reset as standby mode automatically during power up. in addition, the control register architecture of the device constrains that the memory contents can only be changed after specifc command se - quences have completed successfully. in the following, there are several features to protect the system from the accidental write cycles during vcc power-up and power-down or from system noise. ? valid command length checking: the command length will be checked whether it is at byte base and complet - ed on byte boundary. ? write enable (wren) command: wren command is required to set the write enable latch bit (wel) before other command to change data. the wel bit will return to reset stage under following situation: - power-up - wrdi command comple tion - wrsr command comple tion - pp command completion - 4pp command completion - se command completion - be32k command comple tion - be command completion - ce command completion - pgm/ers suspend command completion - softreset command completion - wrscur command com pletion - wpsel command completion - sblk command complet ion - sbulk command compl etion - gblk command comple tion - gbulk command comp letion ? deep power down mode: by entering deep power down mode, the fash device also is under protected from writing all commands except release from deep power down mode command (rdp) and read electronic signature command (res). i. block lock protection - the software protected mode (spm) uses (tb, bp3, bp2, bp1, bp0) bits to allow part of memory to be protected as read only. the protected area defnition is shown as table of "table 2. protected area sizes" , the protected areas are more fexible which may protect various areas by setting value of tb, bp0-bp3 bits. - the hardware protected mode (hpm) uses wp#/sio2 to protect the (bp3, bp2, bp1, bp0) bits and srwd bit. if the system goes into four i/o or qpi mode, the feature of hpm will be disabled. - mx25l643 9e provides individual block (or sector) write protect & unprotect. user may enter the mode with wpsel command and conduct individual block (or sector) write protect with sblk instruction, or sbulk for individual block (or sector) unprotect. under the mode, user may conduct whole chip (all blocks) protect with gblk instruction and unlock the whole chip with gbulk instruction. MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
10 table 2. protected area sizes protected area sizes (tb bit = 0) status bit protect level bp3 bp2 bp1 bp0 64mb 0 0 0 0 0 (none) 0 0 0 1 1 (1block, block 127th) 0 0 1 0 2 (2blocks, block 126th-127th) 0 0 1 1 3 (4blocks, block 124th-127th) 0 1 0 0 4 (8blocks, block 120th-127th) 0 1 0 1 5 (16blocks, block 112th-127th) 0 1 1 0 6 (32blocks, block 96th-127th) 0 1 1 1 7 (64blocks, block 64th-127th) 1 0 0 0 8 (128blocks, protect all) 1 0 0 1 9 (128blocks, protect all) 1 0 1 0 10 (128blocks, protect all) 1 0 1 1 11 (128blocks, protect all) 1 1 0 0 12 (128blocks, protect all) 1 1 0 1 13 (128blocks, protect all) 1 1 1 0 14 (128blocks, protect all) 1 1 1 1 15 (128blocks, protect all) protected area sizes (tb bit = 1) status bit protect level bp3 bp2 bp1 bp0 64mb 0 0 0 0 0 (none) 0 0 0 1 1 (1block, block 0th) 0 0 1 0 2 (2blocks, block 0th-1st) 0 0 1 1 3 (4blocks, block 0th-3rd) 0 1 0 0 4 (8blocks, block 0th-7th) 0 1 0 1 5 (16blocks, block 0th-15th) 0 1 1 0 6 (32blocks, block 0th-31st) 0 1 1 1 7 (64blocks, block 0th-63rd) 1 0 0 0 8 (128blocks, protect all) 1 0 0 1 9 (128blocks, protect all) 1 0 1 0 10 (128blocks, protect all) 1 0 1 1 11 (128blocks, protect all) 1 1 0 0 12 (128blocks, protect all) 1 1 0 1 13 (128blocks, protect all) 1 1 1 0 14 (128blocks, protect all) 1 1 1 1 15 (128blocks, protect all) note: the device is ready to accept a chip erase instruction if, and only if, all block protect (bp3, bp2, bp1, bp0) are 0. MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
11 ii. additional 4k-bit secured otp for unique identifer: to provide 4k-bit one-time program area for setting device unique serial number - which may be set by factory or system maker . - security register bit 0 ind icates whether the chip is locked by factory or not. - to program the 4k-bit secured otp by entering 4k-bit secured otp mode (with enso command), and going through normal program procedure, and then exiting 4k-bit secured otp mode by writing exso com - mand. - customer may lock-dow n the customer lockable secured otp by writing wrscur(write security register) command to set customer lock-down bit1 as "1". please refer to table of "table 8. security register defni - tion" for security register bit defnition and table of "table 3. 4k-bit secured otp defnition" for address range defnition. note: once lock-down whatever by factory or customer, it cannot be changed any more. while in 4k-bit secured otp mode, array access is not allowed. table 3. .elw6hfxuhg273hqlwlrq address range size standard factory lock customer lock xxx000~xxx00f 128-bit esn (electrical serial number) determined by customer xxx010~xxx1ff 3968-bit n/a MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
12 table 4. memory organization block(32k-byte) sector (4k-byte) 2047 7ff000h 7fffffh ? 2040 7f8000h 7f8fffh 2039 7f7000h 7f7fffh ? 2032 7f0000h 7f0fffh 2031 7ef000h 7effffh ? 2024 7e8000h 7e8fffh 2023 7e7000h 7e7fffh ? 2016 7e0000h 7e0fffh 2015 7df000h 7dffffh ? 2008 7d8000h 7d8fffh 2007 7d7000h 7d7fffh ? 2000 7d0000h 7d0fffh 47 02f000h 02ffffh ? 40 028000h 028fffh 39 027000h 027fffh ? 32 020000h 020fffh 31 01f000h 01ffffh ? 24 018000h 018fffh 23 017000h 017fffh ? 16 010000h 010fffh 15 00f000h 00ffffh ? 8 008000h 008fffh 7 007000h 007fffh ? 0 000000h 000fffh 252 251 250 address range 255 254 253 block(64k-byte) 125 2 1 0 127 126 0 5 4 3 2 1 individual block lock/unlock unit:64k-byte individual block lock/unlock unit:64k-byte individual block lock/unlock unit:64k-byte individual 16 sectors lock/unlock unit:4k-byte individual 16 sectors lock/unlock unit:4k-byte 7. memory organization MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
13 8. device operation 1. before a command is issued, status register should be checked to ensure device is ready for the intended op - eration. 2. when incorrect command is inputted to this lsi, this lsi becomes standby mode and keeps the standby mode until next cs# falling edge. in standby mode, so pin of this lsi should be high-z. 3. when correct command is inputted to this lsi, this lsi becomes active mode and keeps the active mode until next cs# rising edge. 4. for standard single data rate serial mode, input data is latched on the rising edge of serial clock(sclk) and data shifts out on the falling edge of sclk. the difference of serial mode 0 and mode 3 is shown as "figure 1. serial modes supported (for normal serial mode)" . 5. for the following instructions: rdid, rdsr, rdscur, read, fast_read, rdsfdp, w4read, 4read, qread, rdblock, res, and qpiid, the shifted-in instruction sequence is followed by a data-out sequence. after any bit of data being shifted out, the cs# can be high. for the following instructions: wren, wrdi, wrsr, se, be, be32k, ce, pp, 4pp, wpsel, sblk, sbulk, gblk, gbulk, suspend, resume, nop, rsten, rst, eqio, rstqio, enso, exso, wrscur, the cs# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. 6. during the progress of write status register, program, erase operation, to access the memory array is ne - glected and not affect the current operation of write status register, program, erase. note: cpol indicates clock polarity of serial master, cpol=1 for sclk high while idle, cpol=0 for sclk low while not transmitting. cpha indicates clock phase. the combination of cpol bit and cpha bit decides which serial mode is supported. figure 1. serial modes supported (for normal serial mode) sclk msb cpha shift in shift out si 0 1 cpol 0 (serial mode 0) (serial mode 3) 1 so sclk msb MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
14 9. hold feature hold# pin signal goes low to hold any serial communications with the device. the hold feature will not stop the operation of write status register, programming, or erasing in progress. the operation of hold requires chip select (cs#) keeping low and starts on falling edge of hold# pin signal while serial clock (sclk) signal is being low (if serial clock signal is not being low, hold operation will not start until serial clock signal being low). the hold condition ends on the rising edge of hold# pin signal while serial clock(sclk) signal is being low( if serial clock signal is not being low, hold operation will not end until serial clock being low). figure 2. hold condition operation hold# cs# sclk hold condition (standard) hold condition (non-standard) the serial data output (so) is high impedance, both serial data input (si) and serial clock (sclk) are don't care during the hold operation. if chip select (cs#) drives high during hold operation, it will reset the internal logic of the device. to re-start communication with chip, the hold# must be at high and cs# must be at low. note: the hold feature is disabled during quad i/o mode. MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
15 10. quad peripheral interface (qpi) read mode qpi protocol enables user to take full advantage of quad i/o serial flash by providing the quad i/o interface in command cycles, address cycles and as well as data output cycles. 10-1. enable qpi mode by issuing 35h command, the qpi mode is enable. figure 3. enable qpi sequence (command 35h) mode 3 sclk sio0 cs# mode 0 234567 35 sio[3:1] 0 1 10-2. reset qpi mode by issuing f5h command, the device is reset to 1-i/o spi mode. figure 4. reset qpi mode (command f5h) sclk sio[3:0] ce# f5 MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
16 10-3. fast qpi read mode (fastrdq) to increase the code transmission speed, the device provides a "fast qpi read mode" (fastrdq). by issuing command code ebh, the fastrdq mode is enable. the number of dummy cycle increase from 4 to 6 cycles. the read cycle frequency will increase from 54mhz to 86mhz. 3 edom sclk sio[3:0] cs# mode 3 a5 a4 a3 a2 a1 a0 x x mode 0 mode 0 msb data out eb h0 l0 h1 l1 h2 l2 h3 l3 x x x x 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 data in 24-bit address (note) figure 5. fast qpi read mode (fastrdq) (command ebh) MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
17 11. command description table 5. command sets read commands i/o 1 1 4 4 4 4 4 read mode spi spi spi spi spi qpi qpi command read (normal read) fast read (fast read data) w4read 4read (4 x i/o read command) qread (1i/4o read command) fast read (fast read data) 4read (4 x i/o read command) 1st byte 03 (hex) 0b (hex) e7 (hex) eb (hex) 6b (hex) 0b (hex) eb (hex) 2nd byte add1(8) add1(8) add1(2) add1(2) add1(8) add1(2) add1(2) 3rd byte add2(8) add2(8) add2(2) add2(2) add2(8) add2(2) add2(2) 4th byte add3(8) add3(8) add3(2) add3(2) add3(8) add3(2) add3(2) 5th byte dummy(8) dummy(4) dummy* dummy(8) dummy(4) dummy* action n bytes read out until cs# goes high n bytes read out until cs# goes high quad i/o read with 4 dummy cycles quad i/o read with confgurable dummy cycles n bytes read out until cs# goes high quad i/o read with confgurable dummy cycles note: * dummy cycle number will be different, depending on the bit7 (dc) setting of confguration register. please refer to "confguration register" table. MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
18 other commands command wren* (write enable) wrdi * (write disable) rdsr * (read status register) rdcr* (read confguration register) wrsr* (write status/ confguration register) 4pp (quad page program) se * (sector erase) 1st byte 06 (hex) 04 (hex) 05 (hex) 15 (hex) 01 (hex) 38 (hex) 20 (hex) 2nd byte values add1 add1 3rd byte values add2 add2 4th byte add3 add3 action sets the (wel) write enable latch bit resets the (wel) write enable latch bit to read out the values of the status register to read out the values of the confguration register to write new values of the confguration/ status register quad input to program the selected page to erase the selected sector command be 32k * (block erase 32kb) be * (block erase 64kb) ce * (chip erase) pp * (page program) dp (deep power down) rdp (release from deep power down) pgm/ers suspend * (suspends program/ erase) 1st byte 52 (hex) d8 (hex) 60 or c7 (hex) 02 (hex) b9 (hex) ab (hex) 75 (hex) 2nd byte add1 add1 add1 3rd byte add2 add2 add2 4th byte add3 add3 add3 action to erase the selected 32kb block to erase the selected 64kb block to erase whole chip to program the selected page enters deep power down mode release from deep power down mode program/erase operation is interrupted by suspend command command pgm/ers resume * (resumes program/ erase) rdid (read identifc- ation) res * (read electronic id) enso * (enter secured otp) 1st byte 7a (hex) 9f (hex) ab (hex) b1 (hex) 2nd byte x 3rd byte x 4th byte x action to continue performing the suspended program/erase sequence outputs jedec id: 1-byte manufacturer id & 2-byte device id to read out 1-byte device id to enter the 4k-bit secured otp mode MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
19 command (byte) exso * (exit secured otp) rdscur * (read security register) wrscur * (write security register) sblk * (single block lock sbulk * (single block unlock) rdblock * (block protect read) gblk * (gang block lock) 1st byte c1 (hex) 2b (hex) 2f (hex) 36 (hex) 39 (hex) 3c (hex) 7e (hex) 2nd byte add1 add1 add1 3rd byte add2 add2 add2 4th byte add3 add3 add3 action to exit the 4k-bit secured otp mode to read value of security register to set the lock- down bit as "1" (once lock- down, cannot be update) individual block (64k-byte) or sector (4k-byte) write protect individual block (64k-byte) or sector (4k-byte) unprotect read individual block or sector write protect status whole chip write protect command (byte) gbulk * (gang block unlock) nop * (no operation) rsten * (reset enable) rst * (reset memory) eqio (enable quad i/o) rstqio (reset quad i/o) qpiid (qpi id read) 1st byte 98 (hex) 00 (hex) 66 (hex) 99 (hex) 35 (hex) f5 (hex) af (hex) 2nd byte 3rd byte 4th byte action whole chip unprotect entering the qpi mode exiting the qpi mode id in qpi interface command (byte) sbl * (set burst length) wpsel * (write protect selection) rdsfdp * 1st byte 77 (hex) 68 (hex) 5a (hex) 2nd byte value add1(8) 3rd byte add2(8) 4th byte add3(8) 5th byte dummy(8) action to set burst length to enter and enable individal block protect mode n bytes read out until cs# goes high note 1: command set highlighted with (*) are supported both in spi and qpi mode. note 2: it is not recommended to adopt any other code not in the command defnition table, which will potentially enter the hidden mode. note 3: before executing rst command, rsten command must be executed. if there is any other command to interfere, the reset operation will be disabled. MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
20 11-1. write enable (wren) the write enable (wren) instruction is for setting write enable latch (wel) bit. for those instructions like pp, 4pp, cp, se, be, be32k, ce, wrsr, sblk, sbulk, gblk and gbulk, which are intended to change the de - vice content, should be set every time after the wren instruction setting the wel bit. the sequence of issuing wren instruction is: cs# goes low sending wren instruction code cs# goes high. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care in spi mode. figure 6. write enable (wren) sequence (command 06) (spi mode) 21 34567 high-z 0 06h command sclk si cs# so figure 7. write enable (wren) sequence (command 06) (qpi mode) sclk sio[3:0] cs# 06h 0 1 command MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
21 11-2. write disable (wrdi) the write disable (wrdi) instruction is for resetting write enable latch (wel) bit. the sequence of issuing wrdi instruction is: cs# goes low sending wrdi instruction code cs# goes high. the wel bit is reset by following situations: - power-up - wrdi command comple tion - wrsr command comple tion - pp command completion - 4pp command completion - se command completion - be32k command comple tion - be command completion - ce command completion - pgm/ers suspend command completion - softreset command completion - wrscur command com pletion - wpsel command completion - sblk command complet ion - sbulk command compl etion - gblk command comple tion - gbulk command comp letion figure 8. write disable (wrdi) sequence (command 04) (spi mode) 21 34567 high-z 0 04h command sclk si cs# so figure 9. write disable (wrdi) sequence (command 04) (qpi mode) sclk sio[3:0] cs# 04h 0 1 command MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
22 figure 10. read identifcation (rdid) sequence (command 9f) (spi mode only) 11-3. read identifcation (rdid) the rdid instruction is for reading the manufacturer id of 1-byte and followed by device id of 2-byte. the ma - cronix manufacturer id is c2(hex), the memory type id is 25(hex) as the frst-byte device id, and the individual device id of second-byte id are listed as table of 7deoh,''hqlwlrq . the sequence of issuing rdid instruction is: cs# goes low sending rdid instruction code 24-bits id data out on so to end rdid operation can use cs# to high at any time during data out. while program/erase operation is in progress, it will not decode the rdid instruction, so there's no effect on the cycle of program/erase operation which is currently in progress. when cs# goes high, the device is at standby stage. 21 345678 9 10 11 12 13 14 15 command 0 manufacturer identification high-z msb 15 14 13 3210 device identification msb 7 6 5 3 2 1 0 16 17 18 28 29 30 31 sclk si cs# so 9fh MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
23 11-4. read status register (rdsr) the rdsr instruction is for reading status register. the read status register can be read at any time (even in program/erase/write status register condition) and continuously. it is recommended to check the write in progress (wip) bit before sending a new instruction when a program, erase, or write status register operation is in progress. the sequence of issuing rdsr instruction is: cs# goes low sending rdsr instruction code status register data out on so. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. figure 11. read status register (rdsr) sequence (command 05) (spi mode) 21 345678 9 10 11 12 13 14 15 command 0 7 6543210 status register out high-z msb 7 6543210 status register out msb 7 sclk si cs# so 05h figure 12. read status register (rdsr) sequence (command 05) (qpi mode) 0 1 3 sclk si o[3:0] cs# 05h 2 h0 l0 msb lsb 4 5 7 h0 l0 6 h0 l0 8 n h1 l1 sta tus byte status byte status byte status byte MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
24 the defnition of the status register bits is as below: wip bit. the write in progress (wip) bit, a volatile bit, indicates whether the device is busy in program/erase/ write status register progress. when wip bit sets to 1, which means the device is busy in program/erase/write status register progress. when wip bit sets to 0, which means the device is not in progress of program/erase/ write status register cycle. wel bit. the write enable latch (wel) bit, a volatile bit, indicates whether the device is set to internal write en - able latch. when wel bit sets to "1", which means the internal write enable latch is set, the device can accept program/erase/write status register instruction. when wel bit sets to 0, which means no internal write enable latch; the device will not accept program/erase/write status register instruction. the program/erase command will be ignored and will reset wel bit if it is applied to a protected memory area. to ensure both wip bit & wel bit are both set to 0 and available for next program/erase/operations, wip bit needs to be confrm to be 0 before polling wel bit. after wip bit confrmed, wel bit needs to be confrm to be 0. bp3, bp2, bp1, bp0 bits. the block protect (bp3, bp2, bp1, bp0) bits, non-volatile bits, indicate the protect - ed area (as defned in "table 2. protected area sizes" ) of the device to against the program/erase instruction without hardware protection mode being set. to write the block protect (bp3, bp2, bp1, bp0) bits requires the write status register (wrsr) instruction to be executed. those bits defne the protected area of the memory to against page program (pp), sector erase (se), block erase (be) and chip erase (ce) instructions (only if all block protect bits set to 0, the ce instruction can be executed). the bp3, bp2, bp1, bp0 bits are "0" as default. which is un-protected. qe bit. the quad enable (qe) bit, non-volatile bit, while it is "0" (factory default), it performs non-quad and wp# is enable. while qe is "1", it performs quad i/o mode and wp# is disabled. in the other word, if the system goes into four i/o mode (qe=1), the feature of hpm will be disabled. while in qpi mode, qe bit is not required for set - ting. srwd bit. the status register write disable (srwd) bit, non-volatile bit, default value is "0". srwd bit is oper - ated together with write protection (wp#/sio2) pin for providing hardware protection mode. the hardware pro - tection mode requires srwd sets to 1 and wp#/sio2 pin signal is low stage. in the hardware protection mode, the write status register (wrsr) instruction is no longer accepted for execution and the srwd bit and block protect bits (bp3, bp2, bp1, bp0) are read only. the srwd bit defaults to be "0". status register note: see the "table 2. protected area sizes" . bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 srwd (status register write protect) qe (quad enable) bp3 (level of protected block) bp2 (level of protected block) bp1 (level of protected block) bp0 (level of protected block) wel (write enable latch) wip (write in progress bit) 1=status register write disable 1= quad enable 0=not quad enable (note 1) (note 1) (note 1) (note 1) 1=write enable 0=not write enable 1=write operation 0=not in write operation non-volatile bit non-volatile bit non-volatile bit non-volatile bit non-volatile bit non-volatile bit volatile bit volatile bit MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
25 confguration register the confguration register is able to change the default status of flash memory. flash memory will be confgured after the cr bit is set. tb bit the top/bottom (tb) bit is a non-volatile otp bit. the top/bottom (tb) bit is used to confgure the block protect area by bp bit (bp3, bp2, bp1, bp0), starting from top or bottom of the memory array. the tb bit is defaulted as 0, which means top area protect. when it is set as 1, the protect area will change to bottom area of the memory device. to write the tb bit requires the write status register (wrsr) instruction to be executed. confguration register bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 dc (dummy cycle) reserved reserved reserved tb (top/bottom selected) reserved reserved reserved (note) x x x 0=top area protect 1=bottom area protect (default=0) x x x volatile bit x x x otp x x x note: see 'xpp&fohdqg)uhtxhqf7deoh , with "don't care" on other reserved confguration registers. dummy cycle and frequency table dc numbers of dummy clock cycles quad i/o fast read 1 8 104 0 (default) 6 86 MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
26 11-5. write status register (wrsr) the wrsr instruction is for changing the values of status register bits and confguration register bits. be - fore sending wrsr instruction, the write enable (wren) instruction must be decoded and executed to set the write enable latch (wel) bit in advance. the wrsr instruction can change the value of block protect (bp3, bp2, bp1, bp0) bits to defne the protected area of memory (as shown in "table 2. protected area sizes" ). the wrsr also can set or reset the quad enable (qe) bit and set or reset the status register write disable (srwd) bit in accordance with write protection (wp#/sio2) pin signal, but has no effect on bit1(wel) and bit0 (wip) of the status register. the wrsr instruction cannot be executed once the hardware protected mode (hpm) is en - tered. the sequence of issuing wrsr instruction is: cs# goes low sending wrsr instruction code status regis - ter data on si cs# goes high. figure 13. write status register (wrsr) sequence (command 01) (spi mode) 21 345678 9 10 11 12 13 14 15 status register in configuration register in 0 msb sclk si cs# so 01h high-z command mode 3 mode 0 16 17 18 19 20 21 22 23 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 note : also supported in qpi mode with command and subsequent input/output in quad i/o mode. figure 14. write status register (wrsr) sequence (command 01) (qpi mode) sclk sio0 cs# c4, c0 sio1 c5, c1 5 4 0 1 2 3 sio2 c6, c2 6 sio3 c7, c3 command status 7 13 12 8 9 10 11 14 15 register in configuration register in MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
27 the cs# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. the self-timed write status register cycle time (tw) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be checked out during the write status register cycle is in progress. the wip sets 1 during the tw timing, and sets 0 when write status register cycle is completed, and the write en - able latch (wel) bit is reset. note: as defned by the values in the block protect (bp3, bp2, bp1, bp0) bits of the status register, as shown in "table 2. protected area sizes" . mode status register condition wp# and srwd bit status memory software protection mode (spm) status register can be written in (wel bit is set to "1") and the srwd, bp0-bp3 bits can be changed wp#=1 and srwd bit=0, or wp#=0 and srwd bit=0, or wp#=1 and srwd=1 the protected area cannot be programmed or erased. hardware protection mode (hpm) the srwd, bp0-bp3 of status register bits cannot be changed wp#=0, srwd bit=1 the protected area cannot be programmed or erased. table 6. protection modes as the table above showing, the summary of the software protected mode (spm) and hardware protected mode (hpm): software protected mode (spm): - when srwd bit=0, no matter wp#/sio2 is low or high, the wren instruction may set the wel bit and can change the values of srwd, bp3, bp2, bp1, bp0. the protected area, which is defned by bp3, bp2, bp1, bp0, is at software protected mode (spm). - when srwd bit=1 and wp#/sio2 is high, the wren instruction may set the wel bit can change the values of srwd, bp3, bp2, bp1, bp0. the protected area, which is defned by bp3, bp2, bp1, bp0, is at software protected mode (spm) hardware protected mode (hpm): - when srwd bit=1, and then wp#/sio2 is low (or wp#/sio2 is low before srwd bit=1), it enters the hard - ware protected mode (hpm). the data of the protected area is protected by software protected mode by bp3, bp2, bp1, bp0 and hardware protected mode by the wp#/sio2 to against data modifcation. note: to exit the hardware protected mode requires wp#/sio2 driving high once the hardware protected mode is entered. if the wp#/sio2 pin is permanently connected to high, the hardware protected mode can never be en - tered; only can use software protected mode via bp3, bp2, bp1, bp0. if the system goes into four i/o or qpi mode, the feature of hpm will be disabled. MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
28 figure 15. wrsr fow wr en co mm and wr sr co mm and write status register data rdsr command wrsr successfully yes yes wrsr fail no start verify ok? wip=0? no rds r command yes wel =1? no rds r command read w el=0, bp[3:0] , q e, and srwd data MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
29 11-6. read data bytes (read) the read instruction is for reading data out. the address is latched on rising edge of sclk, and data shifts out on the falling edge of sclk at a maximum frequency fr. the frst address byte can be at any location. the ad - dress is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single read instruction. the address counter rolls over to 0 when the highest ad - dress has been reached. the sequence of issuing read instruction is: cs# goes low sending read instruction code3-byte address on si data out on so to end read operation can use cs# to high at any time during data out. figure 16. read data bytes (read) sequence (command 03) sclk si cs# so 21 3456789 10 28 29 30 31 32 33 34 35 36 37 38 data out 1 24 add cycles 0 msb msb msb 39 data out 2 03 high-z command d7 a23 a22 a21 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
30 11-7. read data bytes at higher speed (fast_read) the fast_read instruction is for quickly reading data out. the address is latched on rising edge of sclk, and data of each bit shifts out on the falling edge of sclk at a maximum frequency fc. the frst address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single fast_read instruction. the address counter rolls over to 0 when the highest address has been reached. read on spi mode the sequence of issuing fast_read instruction is: cs# goes low sending fast_read instruction code 3-byte address on si1-dummy byte (default) address on si data out on so to end fast_read operation can use cs# to high at any time during data out. (please refer to waveform next page) read on qpi mode the sequence of issuing fast_read instruction in qpi mode is: cs# goes low send - ing fast_read instruction, 2 cycles 24-bit address interleave on sio3, sio2, sio1 & sio04 dummy cyclesdata out interleave on sio3, sio2, sio1 & sio0 to end qpi fast_read operation can use cs# to high at any time during data out. (please refer to waveform next page) while program/erase/write status register cycle is in progress, fast_read instruction is rejected without any impact on the program/erase/write status register current cycle. figure 17. read at higher speed (fast_read) sequence (command 0b) (spi mode) (104mhz) 23 21 345678 9 10 28 29 30 31 22 21 3210 high-z 24 bit address 0 32 33 34 36 37 38 39 40 41 42 43 44 45 46 76543 2 0 1 data out 1 dummy cycle msb 7 6543210 data out 2 msb msb 7 47 76543 2 0 1 35 sclk si cs# so sclk si cs# so 0bh command MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
31 figure 18. read at higher speed (fast_read) sequence (command 0b) (qpi mode) (54mhz) sclk sio(3:0) cs# add add add add add add x x mode 0 msb lsb msb lsb data out 1 data out 2 data in 0bh x x h0 l0 h1 l1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 3 edom 24 bit address command 11-8. quad read mode (qread) the qread instruction enable quad throughput of serial flash in read mode. the address is latched on rising edge of sclk, and data of every four bits (interleave on 4 i/o pins) shift out on the falling edge of sclk at a maximum frequency fq. the frst address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single qread instruction. the address counter rolls over to 0 when the highest address has been reached. once writ - ing qread instruction, the following data out will perform as 4-bit instead of previous 1-bit. the sequence of issuing qread instruction is: cs# goes low sending qread instruction 3-byte address on si 8-bit dummy cycle data out interleave on so3, so2, so1 & so0 to end qread operation can use cs# to high at any time during data out. while program/erase/write status register cycle is in progress, qread instruction is rejected without any im - pact on the program/erase/write status register current cycle. figure 19. quad read mode sequence (command 6b) high impedance 21 345678 0 sclk si/so0 so/so1 cs# 29 9 30 31 32 33 38 39 40 41 42 6b high impedance wp#/so2 high impedance hold#/so3 8 dummy cycles d4 d0 d5 d1 d6 d2 d7 d3 d4 d0 d5 d1 d6 d2 d7 d3 d4 d5 d6 d7 a23 a22 a2 a1 a0 command 24 add cycles data out 1 data out 2 data out 3 ? ? ? MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
32 11-9. 4 x i/o read mode (4read) the 4read instruction enables quad throughput of serial flash in read mode. a quad enable (qe) bit of sta - tus register must be set to "1" before sending the 4read instruction. the address is latched on rising edge of sclk, and data of every four bits (interleave on 4 i/o pins) shift out on the falling edge of sclk at a maximum frequency fq. the frst address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single 4read in - struction. the address counter rolls over to 0 when the highest address has been reached. once writing 4read instruction, the following address/dummy/data out will perform as 4-bit instead of previous 1-bit. 4 x i/o read on spi mode (4read) the sequence of issuing 4read instruction is: cs# goes low sending 4read instruction 24-bit address interleave on sio3, sio2, sio1 & sio0 2+4 dummy cycles (default) data out interleave on sio3, sio2, sio1 & sio0 to end 4read operation can use cs# to high at any time during data out. (please refer to fgure below) w4read instruction (e7) is also available is spi mode for 4 i/o read. the sequence is similar to 4read, but with only 4 dummy cycles. the clock rate runs at 54mhz. 4 x i/o read on qpi mode (4read) the 4read instruction also support on qpi command mode. the se - quence of issuing 4read instruction qpi mode is: cs# goes low sending 4read instruction 24-bit address interleave on sio3, sio2, sio1 & sio0 2+4 dummy cycles (default) data out interleave on sio3, sio2, sio1 & sio0 to end 4read operation can use cs# to high at any time during data out. figure 20. 4 x i/o read mode sequence (command eb) (spi mode) high impedance 21 345678 0 sclk si/sio0 so/sio1 cs# 9 1210 11 13 14 ebh address bit20, bit16..bit0 address bit21, bit17..bit1 p4 p0 p5 p1 p6 p2 p7 p3 data bit4, bit0, bit4.... data bit5 bit1, bit5.... 15 16 17 18 19 20 21 22 23 n high impedance wp#/sio2 address bit22, bit18..bit2 data bit6 bit2, bit6.... high impedance hold#/sio3 address bit23, bit19..bit3 data bit7 bit3, bit7.... 8 bit instruction 6 address cycles performance enhance indicator (note 2) data output congurable dummy cycles (note 3) note: 1. hi-impedance is inhibited for the two clock cycles. 2. p7p3, p6p2, p5p1 & p4p0 (toggling) is inhibited. 3. the confgurable dummy cycle is set by confguration register bit. please see "dummy cycle and fre - tf7 MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
33 figure 21. 4 x i/o read mode sequence (command eb) (qpi mode) 3 edom sclk sio[3:0] cs# mode 3 a5 a4 a3 a2 a1 a0 x x mode 0 mode 0 msb data out eb h0 l0 h1 l1 h2 l2 h3 l3 x x x x 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 data in 24-bit address (note) configurable dummy cycle another sequence of issuing 4read instruction especially useful in random access is : cs# goes low sending 4read instruction 3-bytes address interleave on sio3, sio2, sio1 & sio0 performance enhance toggling bit p[7:0] 4 dummy cycles data out until cs# goes high cs# goes low (reduce 4read instruction) 24-bit random access address (please refer to "figure 22. 4 x i/o read enhance performance mode sequence (command eb) (spi mode)" ). in the performance-enhancing mode (notes of "figure 22. 4 x i/o read enhance performance mode sequence (command eb) (spi mode)" ), p[7:4] must be toggling with p[3:0]; likewise p[7:0]=a5h, 5ah, f0h or 0fh can make this mode continue and reduce the next 4read instruction. once p[7:4] is no longer toggling with p[3:0]; likewise p[7:0]=ffh, 00h, aah or 55h. these commands will reset the performance enhance mode. and after - wards cs# is raised and then lowered, the system then will return to normal operation. while program/erase/write status register cycle is in progress, 4read instruction is rejected without any im - pact on the program/erase/write status register current cycle. MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
34 11-10. performance enhance mode the device could waive the command cycle bits if the two cycle bits after address cycle toggles. (please note "figure 22. 4 x i/o read enhance performance mode sequence (command eb) (spi mode)" ) performance enhance mode is supported in both spi and qpi mode for 4read mode. in qpi mode, ebh, 0bh and spi ebh, e7h commands support enhance mode. after entering enhance mode, following cs# go high, the device will stay in the read mode and treat cs# go low of the frst clock as address instead of command cycle. to exit enhance mode, a new fast read command whose frst two dummy cycles is not toggle then exit. or issue ffh data cycles to exit enhance mode. figure 22. 4 x i/o read enhance performance mode sequence (command eb) (spi mode) high impedance 21 345678 0 sclk si/sio0 so/sio1 cs# 9 1210 11 13 14 ebh address bit20, bit16..bit0 address bit21, bit17..bit1 p4 p0 p5 p1 p6 p2 p7 p3 data bit4, bit0, bit4.... data bit5 bit1, bit5.... 15 16 n+1 ........... ...... ........... ........... n+7 n+9 n+13 17 18 19 20 21 22 23 n high impedance wp#/sio2 address bit22, bit18..bit2 data bit6 bit2, bit6.... high impedance hold#/sio3 address bit23, bit19..bit3 data bit7 bit3, bit7.... 8 bit instruction 6 address cycles performance enhance indicator (note1) data output sclk si/sio0 so/sio1 cs# address bit20, bit16..bit0 address bit21, bit17..bit1 p4 p0 p5 p1 p6 p2 p7 p3 data bit4, bit0, bit4.... data bit5 bit1, bit5.... wp#/sio2 address bit22, bit18..bit2 data bit6 bit2, bit6.... hold#/sio3 address bit23, bit19..bit3 data bit7 bit3, bit7.... 6 address cycles performance enhance indicator (note1) data output congurable dummy cycles (note 2) congurable dummy cycles (note 2) note: 1. performance enhance mode, if p7p3 & p6p2 & p5p1 & p4p0 (toggling), ex: a5, 5a, 0f, if not using performance enhance recommend to keep 1 or 0 in performance enhance indicator. reset the performance enhance mode, if p7=p3 or p6=p2 or p5=p1 or p4=p0, ex: aa, 00, ff 2. the confgurable dummy cycle is set by confguration register bit. please see "dummy cycle and frequency table" MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
35 figure 23. 4 x i/o read enhance performance mode sequence (command eb) (qpi mode) sclk sio[3:0] cs# a5 a4 a3 a2 a1 a0 mode 0 data out data in ebh x p(7:4) p(3:0) x x x h0 l0 h1 l1 configurable dummy cycles (note) performance enhance indicator sclk sio[3:0] cs# a5 a4 a3 a2 a1 a0 mode 0 data out msb lsb msb lsb msb lsb msb lsb 6 address cycles x p(7:4) p(3:0) x x x h0 l0 h1 l1 performance enhance indicator n+1 ............. 3 edom 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 configurable dummy cycles (note) note: the confgurable dummy cycle is set by confguration register bit. please see "dummy cycle and frequency table" MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
36 11-11. performance enhance mode reset to conduct the performance enhance mode reset operation in spi mode, ffh data cycle, 8 clocks, should be issued in 1i/o sequence. in qpi mode, ffffffffh data cycle, 8 clocks, in 4i/o should be issued. if the system controller is being reset during operation, the fash device will return to the standard spi operation. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. figure 24. performance enhance mode reset for fast read quad i/o (spi mode) 21 34567 mode 3 don?t care mode mode 3 mode sclk sio0 cs# sio1 ffh sio2 sio3 mode bit reset for quad i/o don?t care don?t care figure 25. performance enhance mode reset for fast read quad i/o (qpi mode) 21 34567 mode 3 mode mode 3 mode sclk sio[3:0] cs# ffffffffh mode bit reset for quad i/o MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
37 11-12. burst read the device supports burst read in both spi and qpi mode. to set the burst length, following command operation is required issuing command: 77h in the frst byte (8-clocks), following 4 clocks defning wrap around enable with 0h and disable with1h. next 4 clocks is to defne wrap around depth. defnition as following table: the wrap around unit is defned within the 256byte page, with random initial address. its defned as wrap- around mode disable for the default state of the device. to exit wrap around, it is required to issue another 77 command in which data=1xh. otherwise, wrap around status will be retained until power down or reset command. to change wrap around depth, it is requried to issue another 77 command in which data=0xh. qpi 0bh ebh and spi ebh e7h support wrap around feature after wrap around enable. burst read is supported in both spi and qpi mode. the device id default without burst read. 0 cs# sclk sio 77h d7 d6 d5 d4 d3 d2 d1 d0 1 2 3 4 6 7 8 9 10 1 12 13 14 15 5 mode 3 mode 0 spi mode qpi mode 0 cs# sclk sio[3:0] h0 msb lsb l0 77h 1 2 3 mode 3 mode 0 note: msb=most signifcant bit lsb=least signifcant bit data wrap around wrap depth 00h yes 8-byte 01h yes 16-byte 02h yes 32-byte 03h yes 64-byte 1xh no x MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
38 11-13. sector erase (se) the sector erase (se) instruction is for erasing the data of the chosen sector to be "1". the instruction is used for any 4k-byte sector. a write enable (wren) instruction must execute to set the write enable latch (wel) bit before sending the sector erase (se). any address of the sector (see "table 4. memory organization" ) is a valid address for sector erase (se) instruction. the cs# must go high exactly at the byte boundary (the latest eighth of address byte has been latched-in); otherwise, the instruction will be rejected and not executed. the sequence of issuing se instruction is: cs# goes low sending se instruction code 3-byte address on si cs# goes high. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. the self-timed sector erase cycle time (tse) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be checked out during the sector erase cycle is in progress. the wip sets 1 during the tse timing, and sets 0 when sector erase cycle is completed, and the write enable latch (wel) bit is reset. if the sector is protected by bp3~0 (wpsel=0) or by individual lock (wpsel=1), the array data will be protected (no change) and the wel bit still be reset. figure 26. sector erase (se) sequence (command 20) (spi mode) 24 bit address 21 3456789 29 30 31 0 23 22 2 1 0 msb sclk cs# si 20h command figure 27. sector erase (se) sequence (command 20) (qpi mode) sclk sio[3:0] cs# 20h 2 3 5 7 10 msb a20 a16 a12 a8 a4 a0 lsb 4 6 24 bit address command MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
39 11-14. block erase (be) the block erase (be) instruction is for erasing the data of the chosen block to be "1". the instruction is used for 64k-byte block erase operation. a write enable (wren) instruction must execute to set the write enable latch (wel) bit before sending the block erase (be). any address of the block (see "table 4. memory organization" ) is a valid address for block erase (be) instruction. the cs# must go high exactly at the byte boundary (the lat - est eighth of address byte has been latched-in); otherwise, the instruction will be rejected and not executed. the sequence of issuing be instruction is: cs# goes low sending be instruction code 3-byte address on si cs# goes high. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. the self-timed block erase cycle time (tbe) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be checked out during the sector erase cycle is in progress. the wip sets 1 during the tbe timing, and sets 0 when sector erase cycle is completed, and the write enable latch (wel) bit is reset. if the block is protected by bp3~0 (wpsel=0) or by individual lock (wpsel=1), the array data will be protected (no change) and the wel bit still be reset. figure 28. block erase (be) sequence (command d8) (spi mode) 24 bit address 21 3456789 29 30 31 0 23 22 2 0 1 msb sclk cs# si d8h command figure 29. block erase (be) sequence (command d8) (qpi mode) sclk sio[3:0] cs# d8h 2 3 10 msb a20 a16 a12 a8 a4 a0 4 5 6 7 24 bit address command MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
40 11-15. block erase (be32k) the block erase (be32k) instruction is for erasing the data of the chosen block to be "1". the instruction is used for 32k-byte block erase operation. a write enable (wren) instruction must execute to set the write en - able latch (wel) bit before sending the block erase (be32k). any address of the block (see "table 4. memory organization" ) is a valid address for block erase (be32k) instruction. the cs# must go high exactly at the byte boundary (the latest eighth of address byte has been latched-in); otherwise, the instruction will be rejected and not executed. the sequence of issuing be32k instruction is: cs# goes low sending be32k instruction code 3-byte ad - dress on si cs# goes high. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. the self-timed block erase cycle time (tbe32k) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be checked out during the sector erase cycle is in progress. the wip sets 1 during the tbe32k timing, and sets 0 when sector erase cycle is completed, and the write enable latch (wel) bit is reset. if the block is protected by bp3~0 (wpsel=0) or by individual lock (wpsel=1), the array data will be protected (no change) and the wel bit still be reset. figure 30. block erase 32kb (be32k) sequence (command 52) (spi mode) 24 bit address 21 3456789 29 30 31 0 23 22 2 0 1 msb sclk cs# si 52h command figure 31. block erase 32kb (be32k) sequence (command 52) (qpi mode) sclk sio[3:0] cs# 52h 2 3 5 7 10 msb 4 6 24 bit address command a20 a16 a12 a8 a4 a0 MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
41 11-16. chip erase (ce) the chip erase (ce) instruction is for erasing the data of the whole chip to be "1". a write enable (wren) in - struction must execute to set the write enable latch (wel) bit before sending the chip erase (ce). the cs# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. the sequence of issuing ce instruction is: cs# goes low sending ce instruction code cs# goes high. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. the self-timed chip erase cycle time (tce) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be checked out during the chip erase cycle is in progress. the wip sets 1 during the tce timing, and sets 0 when chip erase cycle is completed, and the write enable latch (wel) bit is reset. if the chip is protected the chip erase (ce) instruction will not be executed, but wel will be reset. figure 32. chip erase (ce) sequence (command 60 or c7) (spi mode) 21 34567 0 60h or c7h sclk si cs# command figure 33. chip erase (ce) sequence (command 60 or c7) (qpi mode) sclk sio[3:0] cs# 60h or c7h 0 1 command MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
42 11-17. page program (pp) the page program (pp) instruction is for programming the memory to be "0". a write enable (wren) instruction must execute to set the write enable latch (wel) bit before sending the page program (pp). the device programs only the last 256 data bytes sent to the device. the last address byte (the 8 least signifcant address bits, a7-a0) should be set to 0 for 256 bytes page program. if a7-a0 are not all zero, transmitted data that exceed page length are programmed from the starting address (24-bit address that last 8 bit are all 0) of currently selected page. if the data bytes sent to the device exceeds 256, the last 256 data byte is programmed at the request page and previous data will be disregarded. if the data bytes sent to the device has not exceeded 256, the data will be programmed at the request address of the page. there will be no effort on the other data bytes of the same page. the sequence of issuing pp instruction is: cs# goes low sending pp instruction code 3-byte address on si at least 1-byte on data on si cs# goes high. the cs# must be kept to low during the whole page program cycle; the cs# must go high exactly at the byte boundary (the latest eighth bit of data being latched in), otherwise, the instruction will be rejected and will not be executed. the self-timed page program cycle time (tpp) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be checked out during the page program cycle is in progress. the wip sets 1 during the tpp timing, and sets 0 when page program cycle is completed, and the write enable latch (wel) bit is reset. if the page is protected by bp3~0 (wpsel=0) or by individual lock (wpsel=1), the array data will be protected (no change) and the wel bit will still be reset. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. figure 34. page program (pp) sequence (command 02) (spi mode) 4241 43 44 45 46 47 48 49 50 52 53 54 55 40 23 21 345678 9 10 28 29 30 31 32 33 34 35 22 21 3210 36 37 38 24-bit address 0 76543 2 0 1 data byte 1 39 51 76543 2 0 1 data byte 2 76543 2 0 1 data byte 3 data byte 256 2079 2078 2077 2076 2075 2074 2073 76543 2 0 1 2072 msb msb msb msb msb sclk cs# si sclk cs# si 02h command MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
43 11-18. 4 x i/o page program (4pp) the quad page program (4pp) instruction is for programming the memory to be "0". a write enable (wren) instruction must execute to set the write enable latch (wel) bit and quad enable (qe) bit must be set to "1" before sending the quad page program (4pp). the quad page programming takes four pins: sio0, sio1, sio2, and sio3, which can raise programmer performance and the effectiveness of application of lower clock less than 104mhz. for system with faster clock, the quad page program cannot provide more actual favors, because the required internal page program time is far more than the time data fows in. therefore, we suggest that while executing this command (especially during sending data), user can slow the clock speed down to 104mhz below. the other function descriptions are as same as standard page program. the sequence of issuing 4pp instruction is: cs# goes low sending 4pp instruction code 3-byte address on sio[3:0] at least 1-byte on data on sio[3:0] cs# goes high. if the page is protected by bp3~0 (wpsel=0) or by individual lock (wpsel=1), the array data will be protected (no change) and the wel bit will still be reset. figure 35. 4 x i/o page program (4pp) sequence (command 38) a20 a16 a12 a8 a4 a0 a21 a17 a13 a9 a5 a1 a22 a18 a14 a10 a6 a2 a23 a19 a15 a11 a7 a3 21 3456789 6 add cycles data byte 1 data byte 2 data byte 256 0 sclk cs# si/sio0 so/sio1 hold#/sio3 wp#/sio2 38 command 10 11 12 13 14 15 16 17 524 525 d4 d0 d5 d1 d6 d2 d7 d3 d4 d0 d5 d1 d6 d2 d7 d3 d4 d0 d5 d1 d6 d2 d7 d3 figure 36. page program (pp) sequence (command 02) (qpi mode) 2103 edom sclk sio[3:0] cs# mode 0 data byte 2 data in 02h a5 a4 a3 a2 a1 a0 h0 l0 h1 l1 h2 l2 h3 l3 h255 l255 data byte 1 data byte 3 data byte 4 data byte 256 24 bit address command MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
44 the program/erase function instruction function fow is as follows: figure 37. program/erase flow(1) with read array data wren command program/erase command write program data/address (write erase address) rdsr command read array data (same address of pgm/ers) program/erase successfully yes yes program/erase fail no no start program/erase completed verify ok? wip=0? program/erase another block? yes no rdsr command* yes wel=1? no * * issue rdsr to check bp[3:0]. * if wpsel=1, issue rdblock to check the block status. MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
45 figure 38. program/erase flow(2) without read array data wren command program/erase command write program data/address (write erase address) rdsr command rdscur command program/erase successfully yes no program/erase fail yes regpfail/regefail=1? wip=0? program/erase another block? yes no rdsr command* yes wel=1? no start no program/erase completed * issue rdsr to check bp[3:0]. * if wpsel=1, issue rdblock to check the block status. MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
46 11-19. continuous program mode (cp mode) the cp mode may enhance program performance by automatically increasing address to the next higher ad - dress after each byte data has been programmed. the continuous program (cp) instruction is for multiple bytes program to flash. a write enable (wren) in - struction must execute to set the write enable latch (wel) bit before sending the continuous program (cp) instruction. cs# requires to go high before cp instruction is executing. after cp instruction and address input, two bytes of data is input sequentially from msb(bit7) to lsb(bit0). the frst byte data will be programmed to the initial address range with a0=0 and second byte data with a0=1. if only one byte data is input, the cp mode will not process. if more than two bytes data are input, the additional data will be ignored and only two byte data are valid. any byte to be programmed should be in the erase state (ff) frst. it will not roll over during the cp mode, once the last unprotected address has been reached, the chip will exit cp mode and reset write enable latch bit (wel) as "0" and cp mode bit as "0". please check the wip bit status if it is not in write progress before enter - ing next valid instruction. during cp mode, the valid commands are cp command (ad hex), wrdi command (04 hex), rdsr command (05 hex), and rdscur command (2b hex). and the wrdi command is valid after com - pletion of a cp programming cycle, which means the wip bit=0. the sequence of issuing cp instruction is : cs# goes low sending cp instruction code 3-byte address on si pin two data bytes on si cs# goes high to low sending cp instruction and then continue two data bytes are programmed cs# goes high to low till last desired two data bytes are programmed cs# goes high to low sending wrdi (write disable) instruction to end cp mode send rdsr instruction to verify if cp mode word program ends, or send rdscur to check bit4 to verify if cp mode ends. three methods to detect the completion of a program cycle during cp mode: 1) software method-i: by checking wip bit of status register to detect the completion of cp mode. 2) software method-ii: by waiting for a tbp time out to determine if it may load next valid command or not. 3) hardware method: by writing esry (enable so to output ry/by#) instruction to detect the completion of a program cycle during cp mode. the esry instruction must be executed before cp mode execution. once it is enable in cp mode, the cs# goes low will drive out the ry/by# status on so, "0" indicates busy stage, "1" indicates ready stage, so pin outputs tri-state if cs# goes high. dsry (disable so to output ry/by#) instruction to disable the so to output ry/by# and return to status register data output during cp mode. please note that the esry/dsry commands are not accepted unless the completion of cp mode. if the page is protected by bp3~0 (wpsel=0) or by individual lock (wpsel=1), the array data will be pro - tected (no change) and the wel bit will still be reset. MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
47 notes: (1) during cp mode, the valid commands are cp command (ad hex), wrdi command (04 hex), rdsr command (05 hex), rdscur command (2b hex), rsten command (66 hex) and rst command (99hex). (2) once an internal programming operation begins, cs# goes low will drive the status on the so pin and cs# goes high will return the so pin to tri-state. (3) t o end the cp mode, either reaching the highest unprotected address or sending write disable (wrdi) command (04 hex) may achieve it and then it is recommended to send rdsr command (05 hex) to verify if cp mode is ended. please be noticed that software reset and hardware reset can end the cp mode. cs# sclk 0 1 6 7 8 9 si command ad (hex) 30 31 31 s0 high impedance 32 47 48 status (2) data in 24-bit address byte 0, byte1 0 1 valid command (1) data in byte n-1, byte n 6 7 8 20 21 22 23 0 04 (hex) 24 7 0 7 05 (hex) 8 figure 39. continously program (cp) mode sequence with hardware detection (command ad) MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
48 11-20. deep power-down (dp) the deep power-down (dp) instruction is for setting the device on the minimizing the power consumption (to en - tering the deep power-down mode), the standby current is reduced from isb1 to isb2. the deep power-down mode requires the deep power-down (dp) instruction to enter, during the deep power-down mode, the device is not active and all write/program/erase instructions are ignored. when cs# goes high, it's only in standby mode not deep power-down mode. it's different from standby mode. the sequence of issuing dp instruction is: cs# goes low sending dp instruction code cs# goes high. the sio[3:1] are don't care when during this mode. once the dp instruction is set, all instructions will be ignored except the release from deep power-down mode (rdp) and read electronic signature (res) instruction. (those instructions allow the id being reading out). when power-down, the deep power-down mode automatically stops, and when power-up, the device automatically is in standby mode. for rdp instruction the cs# must go high exactly at the byte boundary (the latest eighth bit of instruction code has been latched-in); otherwise, the instructi on will not be executed. as soon as chip select (cs#) goes high, a delay of tdp is required before entering the deep power-down mode and reducing the current to isb2. figure 40. deep power-down (dp) sequence (command b9) 21 34567 0 t dp deep power-down mode stand-by mode sclk cs# si b9h command MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
49 11-21. release from deep power-down (rdp), read electronic signature (res) the release from deep power-down (rdp) instruction is terminated by driving chip select (cs#) high. when chip select (cs#) is driven high, the device is put in the standby power mode. if the device was not previously in the deep power-down mode, the transition to the standby power mode is immediate. if the device was previ - ously in the deep power-down mode, though, the transition to the standby power mode is delayed by tres2, and chip select (cs#) must remain high for at least tres2(max), as specifed in "table 13. ac character - istics" . once in the standby mode, the device waits to be selected, so that it can receive, decode and execute instructions. res instruction is for reading out the old style of 8-bit electronic signature, whose values are shown as "table 7. . this is not the same as rdid instruction. it is not recommended to use for new design. for new design, please use rdid instruction. even in deep power-down mode, the rdp and res are also allowed to be executed, only except the device is in progress of program/erase/write cycles; there's no effect on the current program/erase/write cycles in progress. the sio[3:1] are don't care when during this mode. the res instruction is ended by cs# goes high after the id been read out at least once. the id outputs repeat - edly if continuously send the additional clock cycles on sclk w hile cs# is at low. if the device was not previous - ly in deep power-down mode, the device transition to standby mode is immediate. if the device was previously in deep power-down mode, there's a delay of tres2 to transit to standby mode, and cs# must remain to high at least tres2(max). once in the standby mode, the device waits to be selected, so it can receive, decode, and execute instruction. the rdp instruction is for releasing from deep power-down mode. figure 41. release from deep power-down and read electronic signature (res) sequence (command ab) 23 21 345678 9 10 28 29 30 31 32 33 34 35 22 21 3210 36 37 38 76543 2 0 1 high-z electronic signature out 3 dummy bytes 0 msb stand-by mode deep power-down mode msb t res2 sclk cs# si so abh command MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
50 11-22. read electronic signature (res) res instruction is for reading out the old style of 8-bit electronic signature, whose values are shown as "table 7. id defnitions" . this is not the same as rdid instruction. it is not recommended to use for new design. for new design, please use rdid instruction. for res instruction, there's no effect on the current program/erase/write cycles in progress. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. the res instruction is ended by cs# goes high after the id been read out at least once. the id outputs repeat - edly if continuously send the additional clock cycles on sclk while cs# is at low . figure 42. read electronic signature (res) sequence (command ab) (spi mode) 23 21 345678 9 10 28 29 30 31 32 33 34 35 22 21 3210 36 37 38 76543 2 0 1 high-z electronic signature out 3 dummy bytes 0 msb msb t res2 sclk cs# si so abh command stand-by mode figure 43. read electronic signature (res) sequence (command ab) (qpi mode) sclk sio[3:0] cs# a5 a4 a3 a2 a1 a0 mode 0 mode 3 msb lsb data out data in h0 l0 stand-by mode 0 abh 1 2 3 4 6 7 5 24 bit address command t res2 MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
51 11-23. qpi id read (qpiid) user can execute this id read instruction to identify the device id and manufacturer id. the sequence of issue qpiid instruction is cs# goes lowsending qpi id instructiondata out on socs# goes high. most signifcant bit (msb) frst. after the command cycle, the device will immediately output data on the falling edge of sclk. the manufacturer id, memory type, and device id data byte will be output continuously , until the cs# goes high. table 7. id defnitions command type MX25L6439E rdid/qpiid manufacturer id memory type memory density c2 25 37 res electronic id 37 11-24. enter secured otp (enso) the enso instruction is for entering the additional 4k-bit secured otp mode. the additional 4k-bit secured otp is independent from main array, which may use to store unique serial number for system identifer. after entering the secured otp mode, and then follow standard read or program procedure to read out the data or up - date data. the secured otp data cannot be updated again once it is lock-down. the sequence of issuing enso instruction is: cs# goes low sending enso instruction to enter secured otp mode cs# goes high. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. please note that wrsr/wrscur/wpsel/sblk/gblk/sbulk/gbulk/ce/be/se/be32k commands are not acceptable during the access of secure otp region, once security otp is locked down, only read related com - mands are valid. 11-25. exit secured otp (exso) the exso instruction is for exiting the additional 4k-bit secured otp mode. the sequence of issuing exso instruction is: cs# goes low sending exso instruction to exit secured otp mode cs# goes high. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
52 11-26. read security register (rdscur) the rdscur instruction is for reading the value of security register. the read security register can be read at any time (even in program/erase/write status register/write security register condition) and continuously. the sequence of issuing rdscur instruction is : cs# goes low sending rdscur instruction security register data out on so cs# goes high. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. 21 345678 9 10 11 12 13 14 15 command 0 7 6543210 security register out security register out high-z msb 7 6543210 msb 7 sclk si cs# so 2b figure 44. read security register (rdscur) sequence (command 2b) (spi mode) the defnition of the security register is as below: secured otp indicator bit. the secured otp indicator bit shows the chip is locked by factory before ex- factory or not. when it is "0", it indicates non-factory lock; "1" indicates factory- lock. lock-down secured otp (ldso) bit. by writing wrscur instruction, the ldso bit may be set to "1" for cus - tomer lock-down purpose. however, once the bit is set to "1" (lock-down), the ldso bit and the 4k-bit secured otp area cannot be updated any more. while it is in 4k-bit secured otp mode, array access is not allowed. program suspend status bit. program suspend bit (psb) indicates the status of program suspend operation. users may use psb to identify the state of fash memory. after the fash memory is suspended by program sus - pend command, psb is set to "1". psb is cleared to "0" after program operation resumes erase suspend status bit. erase suspend bit (esb) indicates the status of erase suspend operation. users may use esb to identify the state of fash memory. after the fash memory is suspended by erase suspend com - mand, esb is set to "1". esb is cleared to "0" after erase operation resumes. MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
53 program fail flag bit. while a program failure happened, the program fail flag bit would be set. if the program operation fails on a protected memory region or locked otp region, this bit will also be set. this bit can be the failure indication of one or more program operations. this fail fag bit will be cleared automatically after the next successful program operation. erase fail flag bit. while an erase failure happened, the erase fail flag bit would be set. if the erase opera - tion fails on a protected memory region or locked otp region, this bit will also be set. this bit can be the failure indication of one or more erase operations. this fail fag bit will be cleared automatically after the next successful erase operation. write protection select bit. the write protection select bit indicates that wpsel has been executed success - fully. once this bit has been set (wpsel=1), all the blocks or sectors will be write-protected after the power- on every time. once wpsel has been set, it cannot be changed again, which means it's only for individual wp mode. under the individual block protection mode (wpsel=1), hardware protection is performed by driving wp#=0. once wp#=0, all array blocks/sectors are protected regardless of the contents of sram lock bits. table 8. security register defnition bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 wpsel e_fail p_fail reserved erase suspend status program suspend status ldso (lock-down 4k-bit se- cured otp) 4k-bit secured otp 0=normal wp mode 1=individual wp mode (default=0) 0=normal erase succeed 1=indicate erase failed (default=0) 0=normal program succeed 1=indicate program failed (default=0) reserved 0=erase is not suspended 1=erase is suspended (default=0) 0=program is not suspended 1=program is suspended (default=0) 0 = not lockdown 1 = lock- down (cannot program/ erase otp) 0 = nonfactory lock 1 = factory lock non-volatile bit volatile bit volatile bit volatile bit volatile bit volatile bit non-volatile bit non-volatile bit otp read only read only read only read only otp read only MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
54 11-27. write security register (wrscur) the wrscur instruction is for changing the values of security register bits. unlike write status register, the wren instruction is not required before sending wrscur instruction. the wrscur instruction may change the values of bit1 (ldso bit) for customer to lock-down the 4k-bit secured otp area. once the ldso bit is set to "1", the secured otp area cannot be updated any more. the sequence of issuing wrscur instruction is :cs# goes low sending wrscur instruction cs# goes high. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. the cs# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed. figure 45. write security register (wrscur) sequence (command 2f) (spi mode) 21 34567 0 2f sclk si cs# command so high-z 11-28. write protection selection (wpsel) there are two write protection methods, (1) bp protection mode (2) individual block protection mode. if wp - sel=0, fash is under bp protection mode. if wpsel=1, fash is under individual block protection mode. the default value of wpsel is 0. wpsel command can be used to set wpsel=1. please note that wpsel is an otp bit. once wpsel is set to 1, there is no chance to recovery wpsel back to 0. if the fash is put on bp mode, the individual block protection mode is disabled. contrarily, if fash is on the individual block protection mode, the bp mode is disabled. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. every time after the system is powered-on, and the security register bit 7 is checked to be wpsel=1, all the blocks or sectors will be write protected by default. user may only unlock the blocks or sectors via sbulk and gbulk instruction. program or erase functions can only be operated after the unlock instruction is conducted. bp protection mode, wpsel=0: array is protected by bp3~bp0 and bp3~bp0 bits are protected by srwd=1 and wp#=0, where srwd is bit 7 of status register that can be set by wrsr command. MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
55 21 34567 0 68 sclk si cs# command individual block protection mode, wpsel=1: blocks are individually protected by their own sram lock bits which are set to 1 after power up. sbulk and sblk command can set sram lock bit to 0 and 1. when the system accepts and executes wpsel instruc - tion, the bit 7 in security register will be set. it will activate sblk, sbulk, rdblock, gblk, gbulk etc instruc - tions to conduct block lock protection and replace the original software protect mode (spm) use (bp3~bp0) indicated block methods. under the individual block protection mode (wpsel=1), hardware protection is per - formed by driving wp#=0. once wp#=0, all array blocks/sectors are protected regardless of the contents of sram lock bits. execution of wren (write enable) instruction is required before issuing wpsel instruction. the sequence of issuing wpsel instruction is: cs# goes low sending wpsel instruction to enter the indi - vidual block protect mode cs# goes high. figure 46. write protection selection (wpsel) sequence (command 68) (spi mode) wpsel instruction function fow is as follows: figure 47. bp and srwd if wpsel=0 64kb 64kb . . . 64kb 64kb bp3 bp2 bp1 bp0 srwd w pb pin (1) bp3~bp0 is used to defne the protection group region. (the protected area size see "table 2. protected area sizes" ) (2) srwd=1 and wpb=0 is used to protect bp3~bp0. in this case, srwd and bp3~bp0 of status register bits can not be changed by wrsr MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
56 figure 48. the individual block lock mode is effective after setting wpsel=1 64kb 4kb 64kb 4kb sram sram sram 4kb 4kb sram uniform 64kb bl oc ks sram sram 4kb sram sbulk / sblk / gbulk / gblk / rdblock ?? ? ? ? ? ? ? bottom 4kbx16 sectors top 4kbx16 sectors ? power-up: all sram bits=1 (all blocks are default protected). all arrays cannot be programmed/erased ? sblk/sbulk(36h/39h): - sblk(36h) : set sram bit=1 (protect) : array can not be programmed /erased - sbulk(39h): set sram bit=0 (unprotect): array can be programmed /erased - all top 4kbx16 sectors and bottom 4kbx16 sectors and other 64kb uniform blocks can be protected and unprotected sram bits individually by sblk/sbulk command set. ? gblk/ gbulk(7eh/98h): - gblk(7eh):set all sram bits=1,whole chip are protected and cannot be programmed / erased. - gbulk(98h):set all sram bits=0,whole chip are unprotected and can be programmed / erased. - all sectors and blocks sram bits of whole chip can be protected and unprotected at one time by gblk/gbulk command set. ? rdblock(3ch): - use rdblock mode to check the sram bits status after sbulk /sblk/gbulk/gblk command set. MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
57 figure 49. wpsel flow rdscur(2bh) command rdsr command rdscur(2bh) command wpsel set successfully yes yes wpsel set fail no start wpsel=1? wip=0? no wpsel disable, block protected by bp[3:0] yes no wpsel=1? wpsel(68h) command wpsel enable. block protected by individual lock (sblk, sbulk, ? etc). MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
58 11-29. single block lock/unlock protection (sblk/sbulk) these instructions are only effective after wpsel was executed. the sblk instruction is for write protection a specifed block(or sector) of memory, using a23-a16 or (a23-a12) address bits to assign a 64kbytes block (or 4k bytes sector) to be protected as read only. the sbulk instruction will cancel the block (or sector) write pro - tection state. this feature allows user to stop protecting the entire block (or sector) through the chip unprotect command (gbulk). the wren (write enable) instruction is required before issuing sblk/sbulk instruction. the sequence of issuing sblk/sbulk instruction is: cs# goes low send sblk/sbulk (36h/39h) instruction send 3 address bytes assign one block (or sector) to be protected on si pin cs# goes high. the cs# must go high exactly at the byte boundary, otherwise the instruction will be rejected and not be execut - ed. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. figure 50. single block lock/unlock protection (sblk/sbulk) sequence (command 36/39) (spi mode) 24 bit address cycles 21 3456789 29 30 31 0 msb sclk cs# si 36/39 command a23 a22 a2 a1 a0 MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
59 sblk/sbulk instruction function fow is as follows: figure 51. block lock flow rdscur(2bh) command start wren command sblk command ( 36h + 24bit address ) rdsr command rdblock command ( 3ch + 24bit address ) block lock successfully yes yes block lock fail no data = ffh ? wip=0? lock another block? block lock completed no yes no no yes wpsel=1? wpsel command MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
60 figure 52. block unlock flow wren command rdscur(2bh) command sbulk command ( 39h + 24bit address ) rdsr command yes wip=0? unlock another block? yes no no yes unlock block completed start wpsel=1? wpsel command MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
61 11-30. read block lock status (rdblock) this instruction is only effective after wpsel was executed. the rdblock instruction is for reading the status of protection lock of a specifed block(or sector), using a23-a16 (or a23-a12) address bits to assign a 64k bytes block (4k bytes sector) and read protection lock status bit which the frst byte of read-out cycle. the status bit is"1" to indicate that this block has been protected, that user can read only but cannot write/program /erase this block. the status bit is "0" to indicate that this block hasn't be protected, and user can read and write this block. the sequence of issuing rdblock instruction is: cs# goes low send rdblock (3ch) instruction send 3 address bytes to assign one block on si pin read block's protection lock status bit on so pin cs# goes high. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. figure 53. read block protection lock status (rdblock) sequence (command 3c) (spi mode) 21 3456789 10 28 29 30 31 32 33 34 35 36 37 38 high-z block protection lock status out 24 add cycles 0 msb msb sclk cs# si so 3c command a23 a22 a21 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 39 MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
62 11-31. gang block lock/unlock (gblk/gbulk) these instructions are only effective after wpsel was executed. the gblk/gbulk instruction is for enable/ disable the lock protection block of the whole chip. the wren (write enable) instruction is required before issuing gblk/gbulk instruction. the sequence of issuing gblk/gbulk instruction is: cs# goes low send gblk/gbulk (7eh/98h) instruc - tion cs# goes high. the cs# must go high exactly at the byte boundary, otherwise, the instruction will be rejected and not be ex - ecuted. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. figure 54. gang block lock/unlock (gblk/gbulk) sequence (command 7e/98) (spi mode) 21 34567 0 7e/98 sclk si cs# command MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
63 11-32. program/ erase suspend/ resume the device allow the interruption of sector-erase, block-erase or page-program operations and conduct other operations. details as follows. to enter the suspend/ resume mode: issuing 75h for suspend; 7ah for resume (spi/qpi all acceptable) read security register bit2 (psb) and bit3 (esb) to check suspend ready information. suspend to suspend ready timing: 20us. resume to another suspend timing: 1ms. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. 11-33. erase suspend erase suspend allow the interruption of all erase operations. after erase suspend, wel bit will be clear, only read related, resume command can be accepted. (including: 03h, 0bh, bbh, ebh, e7h, 9fh, afh, 90h, 05h, 2bh, b1h, c1h, 5ah, 3ch, 7ah, 66h, 77h, 35h, f5h, 00h, abh) for erase suspend to program operation, a write enable (wren) instruction must execute to set the write enable latch (wel) bit before starting the operation. please note that the programming command (38, 02) can be accepted under conditions as follows: the bank is divided into 16 banks in this device, each bank's density is 4mb. while conducting erase suspend in one bank, the programming operation that follows can only be conducted in one of the other banks and cannot be conducted in the bank executing the suspend operation. the boundaries of the banks are illustrated as below table. MX25L6439E bank (4m bit) address range 15 780000h-7fffffh 14 700000h-77ffffh 13 680000h-6fffffh 12 600000h-67ffffh 11 580000h-5fffffh 10 500000h-57ffffh 9 480000h-4fffffh 8 400000h-47ffffh 7 380000h-3fffffh 6 300000h-37ffffh 5 280000h-2fffffh 4 200000h-27ffffh 3 180000h-1fffffh 2 100000h-17ffffh 1 080000h-0fffffh 0 000000h-07ffffh MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
64 please be noticed that software reset command is not accepted after erase suspend command, but user still can issue hardware reset function. after issue erase suspend command, latency time 20us is needed before issue another command. erase suspend bit (esb) indicates the status of erase suspend operation. users may use esb to identify the state of fash memory. after the fash memory is suspended by erase suspend command, esb is set to "1". esb is cleared to "0" after erase operation resumes. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. when esb is issued, the write enable latch (wel) bit will be reset. please refer to "figure 55. suspend to read latency" for suspend to read latency. 11-34. program suspend program suspend allows the interruption of all program operations. after program suspend, wel bit will be cleared, only read related, resume and reset command can be accepted. (including: 03h, 0bh, bbh, ebh, e7h, 9fh, afh, 90h, 05h, 2bh, b1h, c1h, 5ah, 3ch, 7ah, 66h, 99h, 77h, 35h, f5h, 00h, abh ) after issue program suspend command, latency time 20us is needed before issue another command. for "suspend to read", "resume to read", "resume to suspend" timing specifcation please note. program suspend bit (psb) indicates the status of program suspend operation. users may use psb to identify the state of fash memory. after the fash memory is suspended by program suspend command, psb is set to "1". psb is cleared to "0" after program operation resumes both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
65 11-35. write-resume the write operation is being resumed when write-resume instruction issued. esb or psb (suspend status bit) in status register will be changed back to 0 the operation of write-resume is as follows: cs# drives low send write resume command cycle (7ah) drive cs# high. by polling busy bit in status register, the internal write operation status could be checked to be completed or not. the user may also wait the time lag of tse, tbe, tbe32k, tpp for sector-erase, block-erase or page-programming. wren (command "06" is not required to issue before resume. resume to another suspend operation requires latency time of 1ms. when erase suspend is being resumed, the wel bit need to be set again if user desire to conduct the program or erase operation. please note that, if "performance enhance mode" is executed during suspend operation, the device can not be resume. to restart the write command, disable the "performance enhance mode" is required. after the "performance enhance mode" is disable, the write-resume command is effective. figure 55. suspend to read latency cs# program latency : 20us erase latency:20us suspend command [75] read command figure 56. resume to read latency cs# tse/tbe/tbe32k/tpp resume command [7a] read command figure 57. resume to suspend latency cs# 1ms resume command [7a] suspend command [75] MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
66 11-36. no operation (nop) the "no operation" command is only able to terminate the reset enable (rsten) command and will not affect any other command. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. 11-37. software reset (reset-enable (rsten) and reset (rst)) the software reset operation combines two instructions: reset-enable (rsten) command and reset (rst) command. it returns the device to a standby mode. all the volatile bits and settings will be cleared then, which makes the device return to the default status as power on. to execute reset command (rst), the reset-enable (rsten) command must be executed frst to perform the reset operation. if there is any other command to interrupt after the reset-enable command, the reset-enable will be invalid. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. if the reset command is executed during program or erase operation, the operation will be disabled, the data un - der processing could be damaged or lost. the reset time is different depending on the last operation. longer latency time is required to recover from a pro - gram operation than from other operations. figure 58. software reset recovery cs# mode 66 99 stand-by mode trcr trcp trce trcr: 200ns (recovery time from read) trcp: 20us (recovery time from program) trce: 12ms (recovery time from erase) 11-38. reset quad i/o (rstqio) the reset quad i/o instruction, f5h, resets the device to 1-bit spi protocol operation. to execute a reset quad i/o operation, the host drives cs# low, sends the reset quad i/o command cycle (f5h) then, drives cs# high. qpi (2 clocks) command cycle can accept by this instruction. note: for eqio and rstqio commands, cs# high width has to follow "write spec" tshsl for next instruction. MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
67 11-39. read sfdp mode (rdsfdp) the serial flash discoverable parameter (sfdp) standard provides a consistent method of describing the functional and feature capabilities of serial fash devices in a standard set of internal parameter tables. these parameter tables can be interrogated by host system software to enable adjustments needed to accommodate divergent features from multiple vendors. the concept is similar to the one found in the introduction of jedec standard, jesd68 on cfi. the sequence of issuing rdsfdp instruction is same as cs# goes lowsend rdsfdp instruction (5ah)send 3 address bytes on si pinsend 1 dummy byte on si pinread sfdp code on soto end rdsfdp operation can use cs# to high at any time during data out. sfdp is a jedec standard, jesd216. figure 59. read serial flash discoverable parameter (rdsfdp) sequence 23 21 345678 9 10 28 29 30 31 22 21 3210 high-z 24 bit address 0 32 33 34 36 37 38 39 40 41 42 43 44 45 46 76543 2 0 1 data out 1 dummy cycle msb 7 6543210 data out 2 msb msb 7 47 76543 2 0 1 35 sclk si cs# so sclk si cs# so 5ah command MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
68 table 9. signature and parameter identifcation data values description comment add (h) (byte) dw add (bit) data (h/b) (note1) data (h) sfdp signature fixed: 50444653h 00h 07:00 53h 53h 01h 15:08 46h 46h 02h 23:16 44h 44h 03h 31:24 50h 50h sfdp minor revision number start from 00h 04h 07:00 00h 00h sfdp major revision number start from 01h 05h 15:08 01h 01h number of parameter headers this number is 0-based. therefore, 0 indicates 1 parameter header. 06h 23:16 01h 01h unused 07h 31:24 ffh ffh id number (jedec) 00h: it indicates a jedec specifed header. 08h 07:00 00h 00h parameter table minor revision number start from 00h 09h 15:08 00h 00h parameter table major revision number start from 01h 0ah 23:16 01h 01h parameter table length (in double word) how many dwords in the parameter table 0bh 31:24 09h 09h parameter table pointer (ptp) first address of jedec flash parameter table 0ch 07:00 30h 30h 0dh 15:08 00h 00h 0eh 23:16 00h 00h unused 0fh 31:24 ffh ffh id number (macronix manufacturer id) it indicates macronix manufacturer id 10h 07:00 c2h c2h parameter table minor revision number start from 00h 11h 15:08 00h 00h parameter table major revision number start from 01h 12h 23:16 01h 01h parameter table length (in double word) how many dwords in the parameter table 13h 31:24 04h 04h parameter table pointer (ptp) first address of macronix flash parameter table 14h 07:00 60h 60h 15h 15:08 00h 00h 16h 23:16 00h 00h unused 17h 31:24 ffh ffh MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
69 table 10. parameter table (0): jedec flash parameter tables description comment add (h) (byte) dw add (bit) data (h/b) (note1) data (h) block/sector erase sizes 00: reserved, 01: 4kb erase, 10: reserved, 11: not support 4kb erase 30h 01:00 01b e5h write granularity 0: 1byte, 1: 64byte or larger 02 1b write enable instruction required for writing to volatile status registers 0: not required 1: required 00h to be written to the status register 03 0b write enable opcode select for writing to volatile status registers 0: use 50h opcode, 1: use 06h opcode note: if target fash status register is nonvolatile, then bits 3 and 4 must be set to 00b. 04 0b unused contains 111b and can never be changed 07:05 111b 4kb erase opcode 31h 15:08 20h 20h (1-1-2) fast read (note2) 0=not support 1=support 32h 16 0b e0h address bytes number used in addressing fash array 00: 3byte only, 01: 3 or 4byte, 10: 4byte only, 11: reserved 18:17 00b double transfer rate (dtr) clocking 0=not support 1=support 19 0b (1-2-2) fast read 0=not support 1=support 20 0b (1-4-4) fast read 0=not support 1=support 21 1b (1-1-4) fast read 0=not support 1=support 22 1b unused 23 1b unused 33h 31:24 ffh ffh flash memory density 37h:34h 31:00 03ff ffffh (1-4-4) fast read number of wait states (note3) 0 0000b: wait states (dummy clocks) not support 38h 04:00 0 0100b 44h (1-4-4) fast read number of mode bits (note4) 000b: mode bits not support 07:05 010b (1-4-4) fast read opcode 39h 15:08 ebh ebh (1-1-4) fast read number of wait states 0 0000b: wait states (dummy clocks) not support 3ah 20:16 0 1000b 08h (1-1-4) fast read number of mode bits 000b: mode bits not support 23:21 000b (1-1-4) fast read opcode 3bh 31:24 6bh 6bh MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
70 description comment add (h) (byte) dw add (bit) data (h/b) (note1) data (h) (1-1-2) fast read number of wait states 0 0000b: wait states (dummy clocks) not support 3ch 04:00 0 0000b 00h (1-1-2) fast read number of mode bits 000b: mode bits not support 07:05 000b (1-1-2) fast read opcode 3dh 15:08 ffh ffh (1-2-2) fast read number of wait states 0 0000b: wait states (dummy clocks) not support 3eh 20:16 0 0000b 00h (1-2-2) fast read number of mode bits 000b: mode bits not support 23:21 000b (1-2-2) fast read opcode 3fh 31:24 ffh ffh (2-2-2) fast read 0=not support 1=support 40h 00 0b feh unused 03:01 111b (4-4-4) fast read 0=not support 1=support 04 1b unused 07:05 111b unused 43h:41h 31:08 ffh ffh unused 45h:44h 15:00 ffh ffh (2-2-2) fast read number of wait states 0 0000b: wait states (dummy clocks) not support 46h 20:16 0 0000b 00h (2-2-2) fast read number of mode bits 000b: mode bits not support 23:21 000b (2-2-2) fast read opcode 47h 31:24 ffh ffh unused 49h:48h 15:00 ffh ffh (4-4-4) fast read number of wait states 0 0000b: wait states (dummy clocks) not support 4ah 20:16 0 0100b 44h (4-4-4) fast read number of mode bits 000b: mode bits not support 23:21 010b (4-4-4) fast read opcode 4bh 31:24 ebh ebh sector type 1 size sector/block size = 2^n bytes (note5) 0x00b: this sector type doesn't exist 4ch 07:00 0ch 0ch sector type 1 erase opcode 4dh 15:08 20h 20h sector type 2 size sector/block size = 2^n bytes 0x00b: this sector type doesn't exist 4eh 23:16 0fh 0fh sector type 2 erase opcode 4fh 31:24 52h 52h sector type 3 size sector/block size = 2^n bytes 0x00b: this sector type doesn't exist 50h 07:00 10h 10h sector type 3 erase opcode 51h 15:08 d8h d8h sector type 4 size sector/block size = 2^n bytes 0x00b: this sector type doesn't exist 52h 23:16 00h 00h sector type 4 erase opcode 53h 31:24 ffh ffh MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
71 table 11. parameter table (1): macronix flash parameter tables description comment add (h) (byte) dw add (bit) data (h/b) (note1) data (h) vcc supply maximum voltage 2000h=2.000v 2700h=2.700v 3600h=3.600v 61h:60h 07:00 15:08 00h 36h 00h 36h vcc supply minimum voltage 1650h=1.650v 2250h=2.250v 2350h=2.350v 2700h=2.700v 63h:62h 23:16 31:24 00h 27h 00h 27h h/w reset# pin 0=not support 1=support 65h:64h 00 0b f99eh h/w hold# pin 0=not support 1=support 01 1b deep power down mode 0=not support 1=support 02 1b s/w reset 0=not support 1=support 03 1b s/w reset opcode reset enable (66h) should be issued before reset opcode 11:04 1001 1001b (99h) program suspend/resume 0=not support 1=support 12 1b erase suspend/resume 0=not support 1=support 13 1b unused 14 1b wrap-around read mode 0=not support 1=support 15 1b wrap-around read mode opcode 66h 23:16 77h 77h wrap-around read data length 08h:support 8b wrap-around read 16h:8b&16b 32h:8b&16b&32b 64h:8b&16b&32b&64b 67h 31:24 64h 64h individual block lock 0=not support 1=support 6bh:68h 00 1b c8d9h individual block lock bit (volatile/nonvolatile) 0=volatile 1=nonvolatile 01 0b individual block lock opcode 09:02 0011 0110b individual block lock volatile protect bit default protect status 0=protect 1=unprotect 10 0b secured otp 0=not support 1=support 11 1b read lock 0=not support 1=support 12 0b permanent lock 0=not support 1=support 13 0b unused 15:14 11b unused 31:16 ffh ffh unused 6fh:6ch 31:00 ffh ffh MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
72 note 1: h/b is hexadecimal or binary . note 2: (x-y-z) means i/o mode nomenclature used to indicate the number of active pins used for the opcode (x), address (y), and data (z). at the present time, the only valid read sfdp instruction modes are: (1-1-1), (2-2-2), and (4-4-4) note 3: wait states is required dummy clock cycles after the address bits or optional mode bits. note 4: mode bits is optional control bits that follow the address bits. these bits are driven by the system controller if they are specifed. (eg,read performance enhance toggling bits) note 5: 4kb=2^0ch,32kb=2^0fh,64kb=2^10h note 6: all unused and undefned area data is blank ffh. MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
73 12. power-on state the device is at below states when power-up: - standby mode - w rite enable latch (wel) bit is reset the device must not be selected during power-up and power-down stage unless the vcc achieves below cor - rect level: - vcc minimum at power- up stage and then after a delay of tvsl - gnd at power-down please note that a pull-up resistor on cs# may ensure a safe and proper power-up/down level. an internal power-on reset (por) circuit may protect the device from data corruption and inadvertent data change during power up state. for further protection on the device, if the vcc does not reach the vcc minimum level, the correct operation is not guaranteed. the read, write, erase, and program command should be sent after the time delay: - tvsl after vcc reached vcc minimum level the device can accept read command after vcc reached vcc minimum and a time delay of tvsl. note: - to stabilize the vcc level, the vcc rail decoupled by a suitable capacitor close to package pins is recommend - ed. (generally around 0.1uf) MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
74 vss vss-2.0v 20ns 20ns 20ns vcc + 2.0v vcc 20ns 20ns 20ns 13. electrical specifications 13-1. absolute maximum ratings symbol parameter min. typ. max. unit conditions cin input capacitance 6 pf vin = 0v cout output capacitance 8 pf vout = 0v rating value ambient operating temperature industrial grade -40c to 85c storage temperature -65c to 150c applied input voltage -0.5v to vcc+0.5v applied output voltage -0.5v to vcc+0.5v vcc to ground potential -0.5v to 4.0v notice: 1. stresses greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is stress rating only and functional operational sections of this specifcation is not implied. expo - sure to absolute maximum rating conditions for extended period may affect reliability. 2. specifcations contained within the following tables are subject to change. 3. during voltage transitions, all pins may overshoot vss to -2.0v and vcc to +2.0v for periods up to 20ns, see the fgures below. figure 60. maximum negative overshoot waveform 13-2. capacitance ta = 25 c, f = 1.0 mhz figure 61. maximum positive overshoot waveform MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
75 device under test diodes=in3064 or equivalent cl 6.2k ohm 2.7k ohm +3.3v cl=30/15pf including jig capacitance figure 62. input test waveforms and measurement level figure 63. output loading ac measurement level input timing reference level output timing reference level 0.8vcc 0.7vcc 0.3vcc 0.5vcc 0.2vcc note: input pulse rise and fall time are <5ns MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
76 table 12. dc characteristics notes : 1. t ypical values at vcc = 3.3v, t = 25c. these currents are valid for all product versions (package and speeds). 2. t ypical value is calculated by simulation. 3. the value guaranteed by characterization, not 100% tested in production. symbol parameter notes min. typ. max. units test conditions ili input load current 1 2 ua vcc = vcc max, vin = vcc or gnd ilo output leakage current 1 2 ua vcc = vcc max, vout = vcc or gnd isb1 vcc standby current 1 15 50 ua vin = vcc or gnd, cs# = vcc isb2 deep power-down current 1 25 ua vin = vcc or gnd, cs# = vcc icc1 vcc read 1 35 ma f=104mhz (4 x i/o read) sclk=0.1vcc/0.9vcc, so=open 19 ma f=104mhz (1 x i/o read) sclk=0.1vcc/0.9vcc, so=open 25 ma fq=86mhz (4 x i/o read) sclk=0.1vcc/0.9vcc, so=open 10 ma f=33mhz, sclk=0.1vcc/0.9vcc, so=open icc2 vcc program current (pp) 1 15 25 ma program in progress, cs# = vcc icc3 vcc write status register (wrsr) current 15 20 ma program status register in progress, cs#=vcc icc4 vcc sector erase current (se) 1 10 25 ma erase in progress, cs#=vcc icc5 vcc chip erase current (ce) 1 15 25 ma erase in progress, cs#=vcc vil input low voltage -0.5 0.8 v vih input high voltage 0.7vcc vcc+0.4 v vol output low voltage 0.4 v iol = 1.6ma voh output high voltage vcc-0.2 v ioh = -100ua temperature = -40c to 85c for industrial grade MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
77 table 13. ac characteristics symbol alt. parameter min. typ. max. unit fsclk fc clock frequency for the following instructions: fast_read, pp, se, be, ce, res, wren, wrdi, rdid, rdsr, wrsr d.c. 104 mhz frsclk fr clock frequency for read instructions 50 mhz ftsclk fq clock frequency for 4read/qread instructions (4) 86 mhz f4pp clock frequency for 4pp (quad page program) 104 mhz tch(1) tclh clock high time others (fsclk: 104mhz) 4.5 ns normal read (frsclk: 50mhz) 9 ns tcl(1) tcll clock low time others (fsclk) 4.5 ns normal read (frsclk) 9 ns tclch clock rise time (3) (peak to peak) 0.1 v/ns tchcl clock fall time (3) (peak to peak) 0.1 v/ns tslch tcss cs# active setup time (relative to sclk) 4 ns tchsl cs# not active hold time (relative to sclk) 4 ns tdvch tdsu data in setup time 2 ns tchdx tdh data in hold time 3 ns tchsh cs# active hold time (relative to sclk) 4 ns tshch cs# not active setup time (relative to sclk) 4 ns tshsl(3) tcsh cs# deselect time read 15 ns write/erase/program 50 ns tshqz tdis output disable time 2.7v-3.6v 10 ns 3.0v-3.6v 8 ns thlch hold# setup time (relative to sclk) 5 ns tchhh hold# hold time (relative to sclk) 5 ns thhch hold setup time (relative to sclk) 5 ns tchhl hold hold time (relative to sclk) 5 ns thhqx tlz hold to output low-z loading=30pf 2.7v-3.6v 10 ns 3.0v-3.6v 8 ns thlqz thz hold# to output high-z loading=30pf 2.7v-3.6v 10 ns 3.0v-3.6v 8 ns tclqv tv clock low to output valid vcc=2.7v~3.6v loading: 10pf 1 i/o 5 ns 4 i/o 7.5 ns loading: 15pf 1 i/o 6 ns 4 i/o 8 ns loading: 30pf 1 i/o 7 ns 4 i/o 8 ns tclqx tho output hold time 1 ns twhsl write protect setup time 20 ns tshwl write protect hold time 100 ns tdp cs# high to deep power-down mode 10 us tres1 cs# high to standby mode without electronic signature read 100 us tres2 cs# high to standby mode with electronic signature read 100 us temperature = -40c to 85c for industrial grade MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
78 notes: 1. tch + tcl must be greater than or equal to 1/ fc. 2. the value guaranteed by characterization, not 100% tested in production. 3. only applicable as a constraint for a wrsr instruction when sr wd is set at 1. 4. for 4read instruction, when dummy cycle=6 (in both spi & qpi mode), clock rate is 86mhz, and when dum - my cycle=8 (in both spi & qpi mode), clock rate is 104mhz. symbol alt. parameter min. typ. max. unit tw write status register cycle time 40 ms tbp byte-program 12 50 us tpp page program cycle time 0.7 3 ms tse sector erase cycle time (4kb) 30 200 ms tbe32k block erase cycle time (32kb) 0.14 1.6 s tbe block erase cycle time (64kb) 0.25 2 s tce chip erase cycle time 20 80 s twps write protection selection time 1 ms twsr write security register time 1 ms MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
79 figure 64. serial input timing figure 65. output timing 14. timing analysis sclk si cs# msb so tdvch high-z lsb tslch tchdx tchcl tclch tshch tshsl tchsh tchsl lsb addr.lsb in tshqz tch tcl tclqx tclqv tclqx tclqv sclk so cs# si MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
80 figure 66. hold timing high-z 01 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 twhsl tshwl sclk si cs# wp# so figure 67. wp# setup timing and hold timing during wrsr when srwd=1 tchhl thlch thhch tchhh thhqx thlqz sclk so cs# hold# MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
81 14-1. initial delivery state the device is delivered with the memory array erased: all bits are set to 1 (each byte contains ffh). the status register contains 00h (all status register bits are 0). note: the parameter is characterized only. symbol parameter min. max. unit tvsl(1) vcc(min) to cs# low 300 us note: vcc (max.) is 3.6v and vcc (min.) is 2.7v. v cc v cc (min) chip selection is not allowed tvsl time device is fully accessible v cc (max) table 14. power-up timing figure 68. power-up timing MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
82 notes : 1. sampled, not 100% tested . 2. for ac spec tchsl, tslch, tdvch, tchdx, tshsl, tchsh, tshch, tchcl, tclch in the fgure, please refer to "table 13. ac characteristics" . symbol parameter notes min. max. unit tvr vcc rise time 1 20 500000 us/v 15. operating conditions whylfh3rzhu8sdqg3rzhurzq ac timing illustrated in "figure 69. ac timing at device power-up" and "figure 70. power-down sequence" are for the supply voltages and the control signals at device power-up and power-down. if the timing in the fg - ures is ignored, the device will not operate correctly. during power-up and power-down, cs# needs to follow the voltage applied on vcc to keep the device not to be selected. the cs# can be driven low when vcc reach vcc(min.) and wait a period of tvsl. figure 69. 7lplqjdwhylfh3rzhu8s sclk si cs# vcc msb in so tdvch high impedance lsb in tslch tchdx tchcl tclch tshch tshsl tchsh tchsl tvr vcc(min) gnd MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
83 figure 70. power-down sequence cs# sclk vcc during power-down, cs# needs to follow the voltage drop on vcc to avoid mis-operation. MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
84 16. erase and programming performance notes: 1. t ypical program and erase time assumes the following conditions: 25c, 3.3v, and checker board pattern. 2. under worst conditions of 85c and 2.7v . 3. system-level overhead is the time required to execute the frst-bus-cycle sequence for the programming com - mand. 17. data retention min. max. input voltage with respect to gnd on all power pins, si, cs# -1.0v 2 vccmax input voltage with respect to gnd on so -1.0v vcc + 1.0v current -100ma +100ma includes all pins except vcc. test conditions: vcc = 3.0v, one pin at a time. parameter typ. (1) max. (2) unit write status register cycle time 40 ms sector erase time (4kb) 30 200 ms block erase time (32kb) 0.14 1.6 s block erase time (64kb) 0.25 2 s chip erase time 20 80 s byte program time (via page program command) 12 50 us page program time 0.7 3 ms erase/program cycle 100,000 cycles 18. latch-up characteristics parameter condition min. max. unit data retention 55?c 20 years MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
85 19. ordering information part no. clock (mhz) temperature package remark MX25L6439Em2i-10g * 104 -40c~85c 8-sop (200mil) MX25L6439Embi-10g 104 -40c~85c 8-vsop (200mil) * advanced information MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
86 20. part name description mx 25 l m2 i temperature range: i: industrial (-40 c to 85 c) package: m2: 200mil 8-sop mb: 200mil 8-vsop density & mode: 6439e: 64mb standard type type: l: 3v device: 25: serial flash 6439e 10 g option: g: rohs compliant and halogen-free speed: 10: 104mhz MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
87 21. package information MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
88 MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
89 22. revision history revision no. description page date 0.00 1. initial releas ed all jun/22/2012 1.0 1. removed "advanced information" status p4 oct/09/2012 2. updated tslch, tchsl, tchsh, tshch value in ac p75 characteristics table 1.1 1. modifed era se suspend section p62 jan/23/2013 1.2 1. updated par ameters for dc/ac characteristics p4,76,78 nov/06/2013 2. updated era se and programming performance p4,84 3. modifed absolute maximum ratings & capacitance table p74 MX25L6439E p/n: pm1842 rev. 1.2, nov. 06, 2013
except for customized products which has been expressly identifed in the applicable agreement, macronix's products are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or household applications only, and not for use in any applications which may, directly or indirectly, cause death, personal injury, or severe property damages. in the event macronix products are used in contradicted to their target usage above, the buyer shall take any and all actions to ensure said macronix's product qualifed for its actual use in accordance with the applicable laws and regulations; and macronix as well as its suppliers and/or distributors shall be released from any and all liability arisen therefrom. copyright? macronix international co., ltd. 2012~2013. all rights reserved, including the trademarks and tradename thereof, such as macronix, mxic, mxic logo, mx logo, integrated solutions provider, nbit, nbit, nbiit, macronix nbit, eliteflash, hybridnvm, hybridflash, xtrarom, phines, kh logo, be-sonos, ksmc, kingtech, mxsmio, macronix vee, macronix map, rich au dio, rich book, rich tv, and fitcam. the names and brands of third party referred thereto (if any) are for identifcation purposes only . for the contact and order information, please visit macronixs web site at: http://www.macronix.com 90 MX25L6439E macronix international co., ltd. reserves the right to change product and specifcations without notice.

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